bed9efed71
MCSymbolizer::tryAddingSymbolicOperand() overloaded the Size parameter to specify either the instruction size or the operand size depending on the architecture. However, for proper symbolic disassembly on X86, we need to know both sizes, as an instruction can have two operands, and the instruction size cannot be reliably calculated based on the operand offset and its size. Hence, split Size into OpSize and InstSize. For X86, the new interface allows to fix a couple of issues: * Correctly adjust the value of PC-relative operands. * Set operand size to zero when the operand is specified implicitly. Differential Revision: https://reviews.llvm.org/D126101
490 lines
20 KiB
C++
490 lines
20 KiB
C++
//===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/SystemZMCTargetDesc.h"
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#include "SystemZ.h"
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#include "TargetInfo/SystemZTargetInfo.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "systemz-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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class SystemZDisassembler : public MCDisassembler {
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public:
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SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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~SystemZDisassembler() override = default;
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DecodeStatus getInstruction(MCInst &instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static MCDisassembler *createSystemZDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new SystemZDisassembler(STI, Ctx);
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(getTheSystemZTarget(),
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createSystemZDisassembler);
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}
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/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
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/// immediate Value in the MCInst.
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///
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/// @param Value - The immediate Value, has had any PC adjustment made by
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/// the caller.
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/// @param isBranch - If the instruction is a branch instruction
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/// @param Address - The starting address of the instruction
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/// @param Offset - The byte offset to this immediate in the instruction
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/// @param Width - The byte width of this immediate in the instruction
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///
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/// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
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/// called then that function is called to get any symbolic information for the
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/// immediate in the instruction using the Address, Offset and Width. If that
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/// returns non-zero then the symbolic information it returns is used to create
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/// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
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/// returns zero and isBranch is true then a symbol look up for immediate Value
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/// is done and if a symbol is found an MCExpr is created with that, else
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/// an MCExpr with the immediate Value is created. This function returns true
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/// if it adds an operand to the MCInst and false otherwise.
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static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
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uint64_t Address, uint64_t Offset,
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uint64_t Width, MCInst &MI,
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const MCDisassembler *Decoder) {
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return Decoder->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset,
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Width, /*InstSize=*/0);
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}
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static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
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const unsigned *Regs, unsigned Size) {
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assert(RegNo < Size && "Invalid register");
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RegNo = Regs[RegNo];
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if (RegNo == 0)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(RegNo));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
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}
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static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
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}
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static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
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}
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static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16);
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}
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static DecodeStatus
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DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
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}
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static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16);
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}
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static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16);
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}
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static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16);
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}
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static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32);
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}
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static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32);
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}
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static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32);
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}
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static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16);
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}
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static DecodeStatus DecodeCR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SystemZMC::CR64Regs, 16);
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}
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template<unsigned N>
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static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
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if (!isUInt<N>(Imm))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template<unsigned N>
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static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
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if (!isUInt<N>(Imm))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeUImmOperand<1>(Inst, Imm);
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}
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static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeUImmOperand<2>(Inst, Imm);
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}
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static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeUImmOperand<3>(Inst, Imm);
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}
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static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeUImmOperand<4>(Inst, Imm);
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}
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static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeUImmOperand<6>(Inst, Imm);
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}
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static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeUImmOperand<8>(Inst, Imm);
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}
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static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeUImmOperand<12>(Inst, Imm);
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}
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static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeUImmOperand<16>(Inst, Imm);
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}
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static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeUImmOperand<32>(Inst, Imm);
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}
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static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeSImmOperand<8>(Inst, Imm);
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}
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static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeSImmOperand<16>(Inst, Imm);
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}
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static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeSImmOperand<32>(Inst, Imm);
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}
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template <unsigned N>
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static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address, bool isBranch,
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const MCDisassembler *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
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uint64_t Value = SignExtend64<N>(Imm) * 2 + Address;
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if (!tryAddingSymbolicOperand(Value, isBranch, Address, 2, N / 8,
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Inst, Decoder))
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Inst.addOperand(MCOperand::createImm(Value));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodePCDBLOperand<12>(Inst, Imm, Address, true, Decoder);
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}
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static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodePCDBLOperand<16>(Inst, Imm, Address, true, Decoder);
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}
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static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodePCDBLOperand<24>(Inst, Imm, Address, true, Decoder);
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}
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static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodePCDBLOperand<32>(Inst, Imm, Address, true, Decoder);
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}
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static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodePCDBLOperand<32>(Inst, Imm, Address, false, Decoder);
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}
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static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Base = Field >> 12;
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uint64_t Disp = Field & 0xfff;
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assert(Base < 16 && "Invalid BDAddr12");
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Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::createImm(Disp));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Base = Field >> 20;
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uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
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assert(Base < 16 && "Invalid BDAddr20");
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Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Index = Field >> 16;
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uint64_t Base = (Field >> 12) & 0xf;
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uint64_t Disp = Field & 0xfff;
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assert(Index < 16 && "Invalid BDXAddr12");
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Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::createImm(Disp));
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Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Index = Field >> 24;
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uint64_t Base = (Field >> 20) & 0xf;
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uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
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assert(Index < 16 && "Invalid BDXAddr20");
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Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
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Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDLAddr12Len4Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Length = Field >> 16;
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uint64_t Base = (Field >> 12) & 0xf;
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uint64_t Disp = Field & 0xfff;
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assert(Length < 16 && "Invalid BDLAddr12Len4");
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Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::createImm(Disp));
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Inst.addOperand(MCOperand::createImm(Length + 1));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Length = Field >> 16;
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uint64_t Base = (Field >> 12) & 0xf;
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uint64_t Disp = Field & 0xfff;
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assert(Length < 256 && "Invalid BDLAddr12Len8");
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Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::createImm(Disp));
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Inst.addOperand(MCOperand::createImm(Length + 1));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDRAddr12Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Length = Field >> 16;
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uint64_t Base = (Field >> 12) & 0xf;
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uint64_t Disp = Field & 0xfff;
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assert(Length < 16 && "Invalid BDRAddr12");
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Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::createImm(Disp));
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Inst.addOperand(MCOperand::createReg(Regs[Length]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field,
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const unsigned *Regs) {
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uint64_t Index = Field >> 16;
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uint64_t Base = (Field >> 12) & 0xf;
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uint64_t Disp = Field & 0xfff;
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assert(Index < 32 && "Invalid BDVAddr12");
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Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
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Inst.addOperand(MCOperand::createImm(Disp));
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Inst.addOperand(MCOperand::createReg(SystemZMC::VR128Regs[Index]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR32Regs);
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}
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static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR32Regs);
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}
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static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
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}
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static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
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}
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static DecodeStatus
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decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeBDXAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
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}
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static DecodeStatus
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decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
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}
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static DecodeStatus
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decodeBDLAddr64Disp12Len4Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeBDLAddr12Len4Operand(Inst, Field, SystemZMC::GR64Regs);
|
|
}
|
|
|
|
static DecodeStatus
|
|
decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs);
|
|
}
|
|
|
|
static DecodeStatus
|
|
decodeBDRAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
return decodeBDRAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
|
|
}
|
|
|
|
static DecodeStatus
|
|
decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
return decodeBDVAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
|
|
}
|
|
|
|
#include "SystemZGenDisassemblerTables.inc"
|
|
|
|
DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
|
|
ArrayRef<uint8_t> Bytes,
|
|
uint64_t Address,
|
|
raw_ostream &CS) const {
|
|
// Get the first two bytes of the instruction.
|
|
Size = 0;
|
|
if (Bytes.size() < 2)
|
|
return MCDisassembler::Fail;
|
|
|
|
// The top 2 bits of the first byte specify the size.
|
|
const uint8_t *Table;
|
|
if (Bytes[0] < 0x40) {
|
|
Size = 2;
|
|
Table = DecoderTable16;
|
|
} else if (Bytes[0] < 0xc0) {
|
|
Size = 4;
|
|
Table = DecoderTable32;
|
|
} else {
|
|
Size = 6;
|
|
Table = DecoderTable48;
|
|
}
|
|
|
|
// Read any remaining bytes.
|
|
if (Bytes.size() < Size) {
|
|
Size = Bytes.size();
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
// Construct the instruction.
|
|
uint64_t Inst = 0;
|
|
for (uint64_t I = 0; I < Size; ++I)
|
|
Inst = (Inst << 8) | Bytes[I];
|
|
|
|
return decodeInstruction(Table, MI, Inst, Address, this, STI);
|
|
}
|