Previously SIFoldOperands::foldInstOperand would only fold a non-inlinable immediate into a single user, so as not to increase code size by adding the same 32-bit literal operand to many instructions. This patch removes that restriction, so that a non-inlinable immediate will be folded into any number of users. The rationale is: - It reduces the number of registers used for holding constant values, which might increase occupancy. (On the other hand, many of these registers are SGPRs which no longer affect occupancy on GFX10+.) - It reduces ALU stalls between the instruction that loads a constant into a register, and the instruction that uses it. - The above benefits are expected to outweigh any increase in code size. Differential Revision: https://reviews.llvm.org/D114643
97 lines
3.3 KiB
LLVM
97 lines
3.3 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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declare double @fabs(double) readnone
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declare double @llvm.fabs.f64(double) readnone
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declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
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declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
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; FUNC-LABEL: {{^}}v_fabs_f64:
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; SI: v_and_b32
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; SI: s_endpgm
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define amdgpu_kernel void @v_fabs_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%tidext = sext i32 %tid to i64
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%gep = getelementptr double, double addrspace(1)* %in, i64 %tidext
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%val = load double, double addrspace(1)* %gep, align 8
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%fabs = call double @llvm.fabs.f64(double %val)
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store double %fabs, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_f64:
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; SI: s_bitset0_b32
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; SI: s_endpgm
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define amdgpu_kernel void @fabs_f64(double addrspace(1)* %out, double %in) {
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%fabs = call double @llvm.fabs.f64(double %in)
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store double %fabs, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_v2f64:
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; SI: s_bitset0_b32
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; SI: s_bitset0_b32
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; SI: s_endpgm
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define amdgpu_kernel void @fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
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%fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
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store <2 x double> %fabs, <2 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_v4f64:
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; SI: s_bitset0_b32
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; SI: s_bitset0_b32
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; SI: s_bitset0_b32
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; SI: s_bitset0_b32
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; SI: s_endpgm
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define amdgpu_kernel void @fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
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%fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
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store <4 x double> %fabs, <4 x double> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}fabs_fold_f64:
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; SI: s_load_dwordx2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x13
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; SI-NOT: and
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}}
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; SI: s_endpgm
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define amdgpu_kernel void @fabs_fold_f64(double addrspace(1)* %out, [8 x i32], double %in0, [8 x i32], double %in1) {
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%fabs = call double @llvm.fabs.f64(double %in0)
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%fmul = fmul double %fabs, %in1
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store double %fmul, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}fabs_fn_fold_f64:
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; SI: s_load_dwordx2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x13
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; SI-NOT: and
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}}
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; SI: s_endpgm
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define amdgpu_kernel void @fabs_fn_fold_f64(double addrspace(1)* %out, [8 x i32], double %in0, [8 x i32], double %in1) {
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%fabs = call double @fabs(double %in0)
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%fmul = fmul double %fabs, %in1
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store double %fmul, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_free_f64:
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; SI: s_bitset0_b32
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; SI: s_endpgm
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define amdgpu_kernel void @fabs_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc= bitcast i64 %in to double
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%fabs = call double @llvm.fabs.f64(double %bc)
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store double %fabs, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_fn_free_f64:
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; SI: s_bitset0_b32
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; SI: s_endpgm
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define amdgpu_kernel void @fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc= bitcast i64 %in to double
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%fabs = call double @fabs(double %bc)
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store double %fabs, double addrspace(1)* %out
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ret void
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}
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