04fff547e2
Currently the return address ABI registers s[30:31], which fall in the call clobbered register range, are added as a live-in on the function entry to preserve its value when we have calls so that it gets saved and restored around the calls. But the DWARF unwind information (CFI) needs to track where the return address resides in a frame and the above approach makes it difficult to track the return address when the CFI information is emitted during the frame lowering, due to the involvment of understanding the control flow. This patch moves the return address ABI registers s[30:31] into callee saved registers range and stops adding live-in for return address registers, so that the CFI machinery will know where the return address resides when CSR save/restore happen during the frame lowering. And doing the above poses an issue that now the return instruction uses undefined register `sgpr30_sgpr31`. This is resolved by hiding the return address register use by the return instruction through the `SI_RETURN` pseudo instruction, which doesn't take any input operands, until the `SI_RETURN` pseudo gets lowered to the `S_SETPC_B64_return` during the `expandPostRAPseudo()`. As an added benefit, this patch simplifies overall return instruction handling. Note: The AMDGPU CFI changes are there only in the downstream code and another version of this patch will be posted for review for the downstream code. Reviewed By: arsenm, ronlieb Differential Revision: https://reviews.llvm.org/D114652
137 lines
3.4 KiB
LLVM
137 lines
3.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -enable-ipra -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN %s
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; Kernels are not called, so there is no call preserved mask.
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; GCN-LABEL: {{^}}kernel:
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; GCN: flat_store_dword
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define amdgpu_kernel void @kernel(i32 addrspace(1)* %out) #0 {
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entry:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}func:
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; GCN: ; NumVgprs: 8
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define hidden void @func() #1 {
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"() #0
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call:
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; GCN-NOT: buffer_store
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN-NOT: writelane
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; GCN: flat_load_dword v8
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_store
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN-NOT: writelane
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
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; GCN: ; NumSgprs: 37
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; GCN: ; NumVgprs: 9
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define amdgpu_kernel void @kernel_call() #0 {
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%vgpr = load volatile i32, i32 addrspace(1)* undef
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tail call void @func()
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store volatile i32 %vgpr, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}func_regular_call:
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN: flat_load_dword v9
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v9
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; GCN: ; NumSgprs: 34
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; GCN: ; NumVgprs: 10
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define void @func_regular_call() #1 {
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%vgpr = load volatile i32, i32 addrspace(1)* undef
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tail call void @func()
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store volatile i32 %vgpr, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}func_tail_call:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4,
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; GCN-NEXT: s_addc_u32 s5,
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; GCN-NEXT: s_setpc_b64 s[4:5]
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; GCN: ; NumSgprs: 32
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; GCN: ; NumVgprs: 8
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define void @func_tail_call() #1 {
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tail call void @func()
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ret void
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}
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; GCN-LABEL: {{^}}func_call_tail_call:
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; GCN: flat_load_dword v9
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; GCN: s_swappc_b64
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v9
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; GCN: s_setpc_b64
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; GCN: ; NumSgprs: 34
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; GCN: ; NumVgprs: 10
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define void @func_call_tail_call() #1 {
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%vgpr = load volatile i32, i32 addrspace(1)* undef
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tail call void @func()
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store volatile i32 %vgpr, i32 addrspace(1)* undef
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tail call void @func()
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ret void
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}
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; GCN-LABEL: {{^}}void_func_void:
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define void @void_func_void() noinline {
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ret void
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}
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; Make sure we don't get save/restore of FP between calls.
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; GCN-LABEL: {{^}}test_funcx2:
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; GCN: s_getpc_b64
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; GCN-NOT: s32
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; GCN: s_swappc_b64
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; GCN-NOT: s32
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; GCN: s_swappc_b64
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define void @test_funcx2() #0 {
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call void @void_func_void()
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call void @void_func_void()
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ret void
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}
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; GCN-LABEL: {{^}}wombat:
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define weak amdgpu_kernel void @wombat(i32* %arg, i32* %arg2) {
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bb:
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call void @hoge() #0
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ret void
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}
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; Make sure we save/restore the return address around the call.
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; Function Attrs: norecurse
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define internal void @hoge() #2 {
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bb:
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; GCN-LABEL: {{^}}hoge:
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; GCN-DAG: v_writelane_b32 [[CSR_VGPR:v[0-9]+]], s30,
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; GCN-DAG: v_writelane_b32 [[CSR_VGPR]], s31,
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; GCN: s_swappc_b64 s[30:31]
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; GCN-DAG: v_readlane_b32 s30, [[CSR_VGPR]],
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; GCN-DAG: v_readlane_b32 s31, [[CSR_VGPR]],
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; GCN: s_waitcnt vmcnt(0)
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; GCN: s_setpc_b64 s[30:31]
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call void @eggs()
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ret void
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}
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declare dso_local void @eggs()
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attributes #0 = { nounwind }
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attributes #1 = { nounwind noinline "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
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attributes #2 = { norecurse }
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