3eb2281bc0
Previously SIFoldOperands::foldInstOperand would only fold a non-inlinable immediate into a single user, so as not to increase code size by adding the same 32-bit literal operand to many instructions. This patch removes that restriction, so that a non-inlinable immediate will be folded into any number of users. The rationale is: - It reduces the number of registers used for holding constant values, which might increase occupancy. (On the other hand, many of these registers are SGPRs which no longer affect occupancy on GFX10+.) - It reduces ALU stalls between the instruction that loads a constant into a register, and the instruction that uses it. - The above benefits are expected to outweigh any increase in code size. Differential Revision: https://reviews.llvm.org/D114643
277 lines
10 KiB
LLVM
277 lines
10 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}or_v2i32:
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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%result = or <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}or_v4i32:
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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%result = or <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_or_i32:
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; SI: s_or_b32
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define amdgpu_kernel void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%or = or i32 %a, %b
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store i32 %or, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_i32:
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; SI: v_or_b32_e32 v{{[0-9]}}
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define amdgpu_kernel void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) {
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%loada = load i32, i32 addrspace(1)* %a
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%or = or i32 %loada, %b
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store i32 %or, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_or_literal_i32:
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f
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define amdgpu_kernel void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) {
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%or = or i32 %a, 99999
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store i32 %or, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_or_literal_i64:
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; SI: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
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; SI-DAG: s_or_b32 s[[RES_HI:[0-9]+]], s[[HI]], 0xf237b
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; SI-DAG: s_or_b32 s[[RES_LO:[0-9]+]], s[[LO]], 0x3039
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; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_LO]]
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; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_HI]]
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define amdgpu_kernel void @scalar_or_literal_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
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%or = or i64 %a, 4261135838621753
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_or_literal_multi_use_i64:
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; SI: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
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; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xf237b
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; SI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x3039
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; SI: s_or_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]]
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; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x3039
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; SI: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0xf237b
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define amdgpu_kernel void @scalar_or_literal_multi_use_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {
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%or = or i64 %a, 4261135838621753
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store i64 %or, i64 addrspace(1)* %out
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%foo = add i64 %b, 4261135838621753
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store volatile i64 %foo, i64 addrspace(1)* undef
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_or_inline_imm_i64:
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; SI: s_load_dwordx2 s[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
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; SI-NOT: or_b32
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; SI: s_or_b32 s[[VAL_LO]], s[[VAL_LO]], 63
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; SI-NOT: or_b32
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; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[VAL_LO]]
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; SI-NOT: or_b32
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; SI: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[VAL_HI]]
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; SI-NOT: or_b32
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; SI: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]
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define amdgpu_kernel void @scalar_or_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
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%or = or i64 %a, 63
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_or_inline_imm_multi_use_i64:
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; SI-NOT: or_b32
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 63
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; SI-NOT: or_b32
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define amdgpu_kernel void @scalar_or_inline_imm_multi_use_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%or = or i64 %a, 63
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store i64 %or, i64 addrspace(1)* %out
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%foo = add i64 %b, 63
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store volatile i64 %foo, i64 addrspace(1)* undef
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_or_neg_inline_imm_i64:
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; SI-DAG: s_load_dword [[VAL:s[0-9]+]]
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; SI-DAG: s_or_b32 [[VAL]], [[VAL]], -8
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; SI-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], -1{{$}}
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; SI-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[VAL]]
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; SI: buffer_store_dwordx2 v[[[V_LO]]:[[V_HI]]]
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define amdgpu_kernel void @scalar_or_neg_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
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%or = or i64 %a, -8
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_literal_i32:
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; SI: v_or_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
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define amdgpu_kernel void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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%loada = load i32, i32 addrspace(1)* %a, align 4
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%or = or i32 %loada, 65535
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store i32 %or, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_inline_immediate_i32:
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; SI: v_or_b32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}}
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define amdgpu_kernel void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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%loada = load i32, i32 addrspace(1)* %a, align 4
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%or = or i32 %loada, 4
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store i32 %or, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_or_i64:
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; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
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; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
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; SI: s_or_b64
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define amdgpu_kernel void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%or = or i64 %a, %b
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_i64:
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; SI: v_or_b32_e32 v{{[0-9]}}
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; SI: v_or_b32_e32 v{{[0-9]}}
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define amdgpu_kernel void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64, i64 addrspace(1)* %a, align 8
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%loadb = load i64, i64 addrspace(1)* %b, align 8
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%or = or i64 %loada, %loadb
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_vector_or_i64:
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; SI: v_or_b32_e32 v{{[0-9]}}
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; SI: v_or_b32_e32 v{{[0-9]}}
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define amdgpu_kernel void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) {
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%loada = load i64, i64 addrspace(1)* %a
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%or = or i64 %loada, %b
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_i64_loadimm:
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; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
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; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xdf77987f, v[[LO_VREG]]
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; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x146f, v[[HI_VREG]]
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; SI: s_endpgm
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define amdgpu_kernel void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64, i64 addrspace(1)* %a, align 8
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%or = or i64 %loada, 22470723082367
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FIXME: The or 0 should really be removed.
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; FUNC-LABEL: {{^}}vector_or_i64_imm:
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; SI: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
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; SI: v_or_b32_e32 v[[LO_RESULT:[0-9]+]], 8, v[[LO_VREG]]
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; SI-NOT: v_or_b32_e32 {{v[0-9]+}}, 0
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; SI: buffer_store_dwordx2 v[[[LO_RESULT]]:[[HI_VREG]]]
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; SI: s_endpgm
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define amdgpu_kernel void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64, i64 addrspace(1)* %a, align 8
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%or = or i64 %loada, 8
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_i64_neg_inline_imm:
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; SI-DAG: buffer_load_dword v[[LO_VREG:[0-9]+]]
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; SI-DAG: v_or_b32_e32 v[[RES_LO:[0-9]+]], -8, v[[LO_VREG]]
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; SI-DAG: v_mov_b32_e32 v[[RES_HI:[0-9]+]], -1{{$}}
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; SI: buffer_store_dwordx2 v[[[RES_LO]]:[[RES_HI]]]
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; SI: s_endpgm
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define amdgpu_kernel void @vector_or_i64_neg_inline_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64, i64 addrspace(1)* %a, align 8
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%or = or i64 %loada, -8
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_or_i64_neg_literal:
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; SI-DAG: buffer_load_dword v[[LO_VREG:[0-9]+]]
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; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, -1{{$}}
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; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xffffff38, v[[LO_VREG]]
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; SI: buffer_store_dwordx2
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; SI: s_endpgm
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define amdgpu_kernel void @vector_or_i64_neg_literal(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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%loada = load i64, i64 addrspace(1)* %a, align 8
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%or = or i64 %loada, -200
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store i64 %or, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}trunc_i64_or_to_i32:
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; SI: s_load_dword s[[SREG0:[0-9]+]]
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; SI: s_load_dword s[[SREG1:[0-9]+]]
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; SI: s_or_b32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]]
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; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], s[[SRESULT]]
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; SI: buffer_store_dword [[VRESULT]],
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define amdgpu_kernel void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {
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%add = or i64 %b, %a
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%trunc = trunc i64 %add to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}or_i1:
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; EG: OR_INT * {{\** *}}T{{[0-9]+\.[XYZW], PS, PV\.[XYZW]}}
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; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], vcc
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define amdgpu_kernel void @or_i1(i32 addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
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%a = load float, float addrspace(1)* %in0
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%b = load float, float addrspace(1)* %in1
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%acmp = fcmp oge float %a, 0.000000e+00
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%bcmp = fcmp oge float %b, 0.000000e+00
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%or = or i1 %acmp, %bcmp
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%result = zext i1 %or to i32
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_or_i1:
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; SI: s_cmp_eq_u32
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; SI: s_cselect_b64 [[C1:[^,]+]], -1, 0
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; SI: s_cmp_eq_u32
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; SI: s_cselect_b64 [[C2:[^,]+]], -1, 0
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; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], [[C1]], [[C2]]
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define amdgpu_kernel void @s_or_i1(i1 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
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%cmp0 = icmp eq i32 %a, %b
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%cmp1 = icmp eq i32 %c, %d
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%or = or i1 %cmp0, %cmp1
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store i1 %or, i1 addrspace(1)* %out
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ret void
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}
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