3eb2281bc0
Previously SIFoldOperands::foldInstOperand would only fold a non-inlinable immediate into a single user, so as not to increase code size by adding the same 32-bit literal operand to many instructions. This patch removes that restriction, so that a non-inlinable immediate will be folded into any number of users. The rationale is: - It reduces the number of registers used for holding constant values, which might increase occupancy. (On the other hand, many of these registers are SGPRs which no longer affect occupancy on GFX10+.) - It reduces ALU stalls between the instruction that loads a constant into a register, and the instruction that uses it. - The above benefits are expected to outweigh any increase in code size. Differential Revision: https://reviews.llvm.org/D114643
124 lines
5.0 KiB
LLVM
124 lines
5.0 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; When a frame index offset is more than 12-bits, make sure we don't store
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; it in mubuf's offset field.
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; Also, make sure we use the same register for storing the scratch buffer addresss
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; for both stores. This register is allocated by the register scavenger, so we
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; should be able to reuse the same regiser for each scratch buffer access.
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; GCN-LABEL: {{^}}legal_offset_fi:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:4{{$}}
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; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x8004
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; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}
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define amdgpu_kernel void @legal_offset_fi(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) {
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entry:
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%scratch0 = alloca [8192 x i32], addrspace(5)
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%scratch1 = alloca [8192 x i32], addrspace(5)
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%scratchptr0 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 0
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store i32 1, i32 addrspace(5)* %scratchptr0
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%scratchptr1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 0
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store i32 2, i32 addrspace(5)* %scratchptr1
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%cmp = icmp eq i32 %cond, 0
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br i1 %cmp, label %if, label %else
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if:
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%if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset
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%if_value = load i32, i32 addrspace(5)* %if_ptr
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br label %done
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else:
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%else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset
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%else_value = load i32, i32 addrspace(5)* %else_ptr
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br label %done
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done:
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%value = phi i32 [%if_value, %if], [%else_value, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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ret void
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}
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; GCN-LABEL: {{^}}legal_offset_fi_offset:
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; GCN-DAG: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}
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; GCN-DAG: v_mov_b32_e32 [[K8000:v[0-9]+]], 0x8004
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; GCN-DAG: v_add_{{[iu]}}32_e32 [[OFFSET:v[0-9]+]], vcc, 0x8004
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; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offen{{$}}
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define amdgpu_kernel void @legal_offset_fi_offset(i32 addrspace(1)* %out, i32 %cond, i32 addrspace(1)* %offsets, i32 %if_offset, i32 %else_offset) {
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entry:
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%scratch0 = alloca [8192 x i32], addrspace(5)
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%scratch1 = alloca [8192 x i32], addrspace(5)
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%offset0 = load i32, i32 addrspace(1)* %offsets
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%scratchptr0 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %offset0
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store i32 %offset0, i32 addrspace(5)* %scratchptr0
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%offsetptr1 = getelementptr i32, i32 addrspace(1)* %offsets, i32 1
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%offset1 = load i32, i32 addrspace(1)* %offsetptr1
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%scratchptr1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %offset1
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store i32 %offset1, i32 addrspace(5)* %scratchptr1
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%cmp = icmp eq i32 %cond, 0
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br i1 %cmp, label %if, label %else
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if:
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%if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset
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%if_value = load i32, i32 addrspace(5)* %if_ptr
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br label %done
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else:
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%else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset
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%else_value = load i32, i32 addrspace(5)* %else_ptr
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br label %done
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done:
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%value = phi i32 [%if_value, %if], [%else_value, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}neg_vaddr_offset_inbounds:
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; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 16, v{{[0-9]+}}
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; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], 0 offen{{$}}
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define amdgpu_kernel void @neg_vaddr_offset_inbounds(i32 %offset) {
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entry:
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%array = alloca [8192 x i32], addrspace(5)
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%ptr_offset = add i32 %offset, 4
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%ptr = getelementptr inbounds [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %ptr_offset
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store i32 0, i32 addrspace(5)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}neg_vaddr_offset:
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; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 16, v{{[0-9]+}}
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; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], 0 offen{{$}}
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define amdgpu_kernel void @neg_vaddr_offset(i32 %offset) {
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entry:
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%array = alloca [8192 x i32], addrspace(5)
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%ptr_offset = add i32 %offset, 4
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%ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %ptr_offset
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store i32 0, i32 addrspace(5)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}pos_vaddr_offset:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:20
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define amdgpu_kernel void @pos_vaddr_offset(i32 addrspace(1)* %out, i32 %offset) {
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entry:
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%array = alloca [8192 x i32], addrspace(5)
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%ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 4
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store i32 0, i32 addrspace(5)* %ptr
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%load_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %offset
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%val = load i32, i32 addrspace(5)* %load_ptr
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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