6ddf2a824d
As older waves execute long sequences of VALU instructions, this may prevent younger waves from address calculation and then issuing their VMEM loads, which in turn leads the VALU unit to idle. This patch tries to prevent this by temporarily raising the wave's priority. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D124246
154 lines
4.6 KiB
LLVM
154 lines
4.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -amdgpu-set-wave-priority=true -o - %s | \
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; RUN: FileCheck %s
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; CHECK-LABEL: no_setprio:
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; CHECK-NOT: s_setprio
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; CHECK: ; return to shader part epilog
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define amdgpu_ps <2 x float> @no_setprio() {
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ret <2 x float> <float 0.0, float 0.0>
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}
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; CHECK-LABEL: vmem_in_exit_block:
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; CHECK: s_setprio 3
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; CHECK: buffer_load_dwordx2
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; CHECK-NEXT: s_setprio 0
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; CHECK: ; return to shader part epilog
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define amdgpu_ps <2 x float> @vmem_in_exit_block(<4 x i32> inreg %p) {
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%v = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 0, i32 0)
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ret <2 x float> %v
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}
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; CHECK-LABEL: branch:
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; CHECK: s_setprio 3
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; CHECK: s_cbranch_scc0 [[A:.*]]
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; CHECK: {{.*}}: ; %b
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; CHECK: buffer_load_dwordx2
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; CHECK-NEXT: s_setprio 0
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; CHECK: s_branch [[EXIT:.*]]
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; CHECK: [[A]]: ; %a
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; CHECK-NEXT: s_setprio 0
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; CHECK: s_branch [[EXIT]]
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; CHECK-NEXT: [[EXIT]]:
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define amdgpu_ps <2 x float> @branch(<4 x i32> inreg %p, i32 inreg %i) {
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%cond = icmp eq i32 %i, 0
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br i1 %cond, label %a, label %b
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a:
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ret <2 x float> <float 0.0, float 0.0>
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b:
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%v = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 0, i32 0)
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ret <2 x float> %v
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}
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; CHECK-LABEL: setprio_follows_setprio:
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; CHECK: s_setprio 3
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; CHECK: buffer_load_dwordx2
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; CHECK: s_cbranch_scc1 [[C:.*]]
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; CHECK: {{.*}}: ; %a
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; CHECK: buffer_load_dwordx2
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; CHECK-NEXT: s_setprio 0
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; CHECK: s_cbranch_scc1 [[C]]
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; CHECK: {{.*}}: ; %b
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; CHECK-NOT: s_setprio
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; CHECK: s_branch [[EXIT:.*]]
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; CHECK: [[C]]: ; %c
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; CHECK-NEXT: s_setprio 0
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; CHECK: s_branch [[EXIT]]
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; CHECK: [[EXIT]]:
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define amdgpu_ps <2 x float> @setprio_follows_setprio(<4 x i32> inreg %p, i32 inreg %i) {
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entry:
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%v1 = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 0, i32 0)
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%cond1 = icmp ne i32 %i, 0
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br i1 %cond1, label %a, label %c
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a:
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%v2 = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 1, i32 0)
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%cond2 = icmp ne i32 %i, 1
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br i1 %cond2, label %b, label %c
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b:
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ret <2 x float> %v2
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c:
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%v3 = phi <2 x float> [%v1, %entry], [%v2, %a]
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%v4 = fadd <2 x float> %v1, %v3
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ret <2 x float> %v4
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}
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; CHECK-LABEL: loop:
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; CHECK: {{.*}}: ; %entry
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; CHECK: s_setprio 3
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; CHECK-NOT: s_setprio
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; CHECK: [[LOOP:.*]]: ; %loop
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; CHECK-NOT: s_setprio
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; CHECK: buffer_load_dwordx2
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; CHECK-NOT: s_setprio
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; CHECK: s_cbranch_scc1 [[LOOP]]
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; CHECK-NEXT: {{.*}}: ; %exit
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; CHECK-NEXT: s_setprio 0
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define amdgpu_ps <2 x float> @loop(<4 x i32> inreg %p) {
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entry:
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br label %loop
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loop:
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%i = phi i32 [0, %entry], [%i2, %loop]
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%sum = phi <2 x float> [<float 0.0, float 0.0>, %entry], [%sum2, %loop]
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%i2 = add i32 %i, 1
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%v = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 %i, i32 0, i32 0, i32 0)
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%sum2 = fadd <2 x float> %sum, %v
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%cond = icmp ult i32 %i2, 5
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br i1 %cond, label %loop, label %exit
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exit:
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ret <2 x float> %sum2
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}
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; CHECK-LABEL: edge_split:
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; CHECK: s_setprio 3
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; CHECK: buffer_load_dwordx2
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; CHECK-NOT: s_setprio
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; CHECK: s_cbranch_scc1 [[ANOTHER_LOAD:.*]]
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; CHECK: {{.*}}: ; %loop.preheader
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; CHECK-NEXT: s_setprio 0
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; CHECK: [[LOOP:.*]]: ; %loop
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; CHECK-NOT: s_setprio
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; CHECK: s_cbranch_scc1 [[LOOP]]
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; CHECK {{.*}}: ; %exit
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; CHECK-NOT: s_setprio
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; CHECK: s_branch [[RET:.*]]
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; CHECK: [[ANOTHER_LOAD]]: ; %another_load
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; CHECK: buffer_load_dwordx2
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; CHECK-NEXT: s_setprio 0
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; CHECK: s_branch [[RET]]
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; CHECK: [[RET]]:
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define amdgpu_ps <2 x float> @edge_split(<4 x i32> inreg %p, i32 inreg %x) {
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entry:
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%v = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 0, i32 0)
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%cond = icmp ne i32 %x, 0
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br i1 %cond, label %loop, label %another_load
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loop:
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%i = phi i32 [0, %entry], [%i2, %loop]
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%mul = phi <2 x float> [%v, %entry], [%mul2, %loop]
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%i2 = add i32 %i, 1
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%mul2 = fmul <2 x float> %mul, %v
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%cond2 = icmp ult i32 %i2, 5
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br i1 %cond2, label %loop, label %exit
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exit:
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ret <2 x float> %mul2
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another_load:
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%v2 = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %p, i32 0, i32 0, i32 1, i32 0)
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%sum = fadd <2 x float> %v, %v2
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ret <2 x float> %sum
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}
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declare <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32>, i32, i32, i32, i32) nounwind
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