da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
142 lines
6.2 KiB
LLVM
142 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Test that when extracting the same unknown vector index from an
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; insertelement the dynamic indexing is folded away.
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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; No dynamic indexing required
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define amdgpu_kernel void @extract_insert_same_dynelt_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %val, i32 %idx) #1 {
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; GCN-LABEL: extract_insert_same_dynelt_v4i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; GCN-NEXT: s_load_dword s0, s[0:1], 0xd
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, 0
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; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: v_mov_b32_e32 v2, s0
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; GCN-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
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; GCN-NEXT: s_endpgm
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%id.ext = sext i32 %id to i64
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%gep.in = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %in, i64 %id.ext
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%gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %id.ext
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%vec = load <4 x i32>, <4 x i32> addrspace(1)* %gep.in
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%insert = insertelement <4 x i32> %vec, i32 %val, i32 %idx
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%extract = extractelement <4 x i32> %insert, i32 %idx
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store i32 %extract, i32 addrspace(1)* %gep.out
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ret void
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}
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define amdgpu_kernel void @extract_insert_different_dynelt_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %val, i32 %idx0, i32 %idx1) #1 {
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; GCN-LABEL: extract_insert_different_dynelt_v4i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
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; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, 0
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; GCN-NEXT: v_lshlrev_b32_e32 v4, 4, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[4:5], s[10:11]
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; GCN-NEXT: v_mov_b32_e32 v5, 0
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; GCN-NEXT: buffer_load_dwordx4 v[1:4], v[4:5], s[4:7], 0 addr64
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; GCN-NEXT: s_load_dword s14, s[0:1], 0xf
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; GCN-NEXT: s_cmp_eq_u32 s13, 3
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; GCN-NEXT: s_cselect_b64 vcc, -1, 0
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; GCN-NEXT: s_cmp_eq_u32 s13, 2
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; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
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; GCN-NEXT: s_cmp_eq_u32 s13, 1
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; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0
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; GCN-NEXT: s_cmp_eq_u32 s13, 0
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; GCN-NEXT: v_lshlrev_b32_e32 v6, 2, v0
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; GCN-NEXT: v_mov_b32_e32 v0, s12
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; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_eq_u32 s14, 1
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; GCN-NEXT: v_mov_b32_e32 v7, v5
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; GCN-NEXT: s_mov_b64 s[10:11], s[6:7]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
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; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v0, s[0:1]
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; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v0, s[2:3]
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; GCN-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[4:5]
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; GCN-NEXT: s_cselect_b64 vcc, -1, 0
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; GCN-NEXT: s_cmp_eq_u32 s14, 2
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; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GCN-NEXT: s_cselect_b64 vcc, -1, 0
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; GCN-NEXT: s_cmp_eq_u32 s14, 3
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; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
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; GCN-NEXT: s_cselect_b64 vcc, -1, 0
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; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
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; GCN-NEXT: buffer_store_dword v0, v[6:7], s[8:11], 0 addr64
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; GCN-NEXT: s_endpgm
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%id.ext = sext i32 %id to i64
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%gep.in = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %in, i64 %id.ext
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%gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %id.ext
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%vec = load <4 x i32>, <4 x i32> addrspace(1)* %gep.in
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%insert = insertelement <4 x i32> %vec, i32 %val, i32 %idx0
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%extract = extractelement <4 x i32> %insert, i32 %idx1
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store i32 %extract, i32 addrspace(1)* %gep.out
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ret void
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}
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define amdgpu_kernel void @extract_insert_same_elt2_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %val, i32 %idx) #1 {
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; GCN-LABEL: extract_insert_same_elt2_v4i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; GCN-NEXT: s_load_dword s0, s[0:1], 0xd
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, 0
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; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: v_mov_b32_e32 v2, s0
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; GCN-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
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; GCN-NEXT: s_endpgm
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%id.ext = sext i32 %id to i64
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%gep.in = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %in, i64 %id.ext
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%gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %id.ext
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%vec = load <4 x i32>, <4 x i32> addrspace(1)* %gep.in
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%insert = insertelement <4 x i32> %vec, i32 %val, i32 %idx
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%extract = extractelement <4 x i32> %insert, i32 %idx
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store i32 %extract, i32 addrspace(1)* %gep.out
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ret void
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}
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define amdgpu_kernel void @extract_insert_same_dynelt_v4f32(float addrspace(1)* %out, <4 x float> addrspace(1)* %in, float %val, i32 %idx) #1 {
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; GCN-LABEL: extract_insert_same_dynelt_v4f32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; GCN-NEXT: s_load_dword s8, s[0:1], 0xd
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, 0
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; GCN-NEXT: v_lshlrev_b32_e32 v4, 4, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[0:1], s[6:7]
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; GCN-NEXT: v_mov_b32_e32 v5, 0
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; GCN-NEXT: buffer_load_dwordx4 v[1:4], v[4:5], s[0:3], 0 addr64 glc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_mov_b64 s[6:7], s[2:3]
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; GCN-NEXT: v_lshlrev_b32_e32 v4, 2, v0
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; GCN-NEXT: v_mov_b32_e32 v0, s8
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; GCN-NEXT: buffer_store_dword v0, v[4:5], s[4:7], 0 addr64
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; GCN-NEXT: s_endpgm
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%id.ext = sext i32 %id to i64
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%gep.in = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %in, i64 %id.ext
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%gep.out = getelementptr inbounds float, float addrspace(1)* %out, i64 %id.ext
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%vec = load volatile <4 x float>, <4 x float> addrspace(1)* %gep.in
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%insert = insertelement <4 x float> %vec, float %val, i32 %idx
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%extract = extractelement <4 x float> %insert, i32 %idx
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store float %extract, float addrspace(1)* %gep.out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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