335e8bf100
This patch changes the PowerPC backend to generate VSX load/store instructions for all vector loads/stores on Power8 and earlier (LE) instead of VMX load/store instructions. The reason for this change is because VMX instructions require the vector to be 16-byte aligned. So, a vector load/store will fail with VMX instructions if the vector is misaligned. Also, `gcc` generates VSX instructions in this situation which allow for unaligned access but require a swap instruction after loading/before storing. This is not an issue for BE because we already emit VSX instructions since no swap is required. And this is not an issue on Power9 and up since we have access to `lxv[x]`/`stxv[x]` which allow for unaligned access and do not require swaps. This patch also delays the VSX load/store for LE combines until after LegalizeOps to prioritize other load/store combines. Reviewed By: #powerpc, stefanp Differential Revision: https://reviews.llvm.org/D127309
277 lines
9.7 KiB
LLVM
277 lines
9.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-LE
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-BE
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; RUN: opt --passes=sroa,loop-vectorize,loop-unroll,instcombine -S \
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; RUN: -vectorizer-maximize-bandwidth --mtriple=powerpc64le-- -mcpu=pwr10 < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-OPT
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target datalayout = "e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512"
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define dso_local signext i32 @test_32byte_vector() nounwind {
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; CHECK-LE-LABEL: test_32byte_vector:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mflr r0
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; CHECK-LE-NEXT: std r30, -16(r1)
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; CHECK-LE-NEXT: mr r30, r1
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; CHECK-LE-NEXT: std r0, 16(r1)
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; CHECK-LE-NEXT: clrldi r0, r1, 59
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; CHECK-LE-NEXT: subfic r0, r0, -96
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; CHECK-LE-NEXT: stdux r1, r1, r0
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; CHECK-LE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-LE-NEXT: addis r4, r2, .LCPI0_1@toc@ha
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; CHECK-LE-NEXT: addi r3, r3, .LCPI0_0@toc@l
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; CHECK-LE-NEXT: addi r4, r4, .LCPI0_1@toc@l
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; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
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; CHECK-LE-NEXT: lxvd2x vs1, 0, r4
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; CHECK-LE-NEXT: addi r4, r1, 48
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; CHECK-LE-NEXT: addi r3, r1, 32
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; CHECK-LE-NEXT: stxvd2x vs0, 0, r4
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; CHECK-LE-NEXT: stxvd2x vs1, 0, r3
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; CHECK-LE-NEXT: bl test
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; CHECK-LE-NEXT: nop
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; CHECK-LE-NEXT: lwa r3, 32(r1)
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; CHECK-LE-NEXT: mr r1, r30
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; CHECK-LE-NEXT: ld r0, 16(r1)
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; CHECK-LE-NEXT: ld r30, -16(r1)
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; CHECK-LE-NEXT: mtlr r0
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_32byte_vector:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mflr r0
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; CHECK-BE-NEXT: std r30, -16(r1)
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; CHECK-BE-NEXT: std r0, 16(r1)
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; CHECK-BE-NEXT: clrldi r0, r1, 59
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; CHECK-BE-NEXT: mr r30, r1
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; CHECK-BE-NEXT: subfic r0, r0, -192
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; CHECK-BE-NEXT: stdux r1, r1, r0
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; CHECK-BE-NEXT: lis r3, -8192
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; CHECK-BE-NEXT: li r4, 5
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; CHECK-BE-NEXT: lis r5, -16384
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; CHECK-BE-NEXT: lis r6, -32768
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; CHECK-BE-NEXT: ori r3, r3, 1
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; CHECK-BE-NEXT: rldic r4, r4, 32, 29
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; CHECK-BE-NEXT: ori r5, r5, 1
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; CHECK-BE-NEXT: ori r6, r6, 1
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; CHECK-BE-NEXT: rldic r3, r3, 3, 29
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; CHECK-BE-NEXT: ori r4, r4, 6
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; CHECK-BE-NEXT: rldic r5, r5, 2, 30
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; CHECK-BE-NEXT: rldic r6, r6, 1, 31
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; CHECK-BE-NEXT: std r3, 152(r1)
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; CHECK-BE-NEXT: addi r3, r1, 128
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; CHECK-BE-NEXT: std r4, 144(r1)
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; CHECK-BE-NEXT: std r5, 136(r1)
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; CHECK-BE-NEXT: std r6, 128(r1)
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; CHECK-BE-NEXT: bl test
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; CHECK-BE-NEXT: nop
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; CHECK-BE-NEXT: lwa r3, 128(r1)
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; CHECK-BE-NEXT: mr r1, r30
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; CHECK-BE-NEXT: ld r0, 16(r1)
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; CHECK-BE-NEXT: ld r30, -16(r1)
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; CHECK-BE-NEXT: mtlr r0
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; CHECK-BE-NEXT: blr
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entry:
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%a = alloca <8 x i32>, align 32
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%0 = bitcast <8 x i32>* %a to i8*
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call void @llvm.lifetime.start.p0i8(i64 32, i8* %0)
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store <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>, <8 x i32>* %a, align 32
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call void @test(<8 x i32>* %a)
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%1 = load <8 x i32>, <8 x i32>* %a, align 32
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%vecext = extractelement <8 x i32> %1, i32 0
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%2 = bitcast <8 x i32>* %a to i8*
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call void @llvm.lifetime.end.p0i8(i64 32, i8* %2)
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ret i32 %vecext
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}
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define dso_local signext i32 @test_32byte_aligned_vector() nounwind {
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; CHECK-LE-LABEL: test_32byte_aligned_vector:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mflr r0
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; CHECK-LE-NEXT: std r30, -16(r1)
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; CHECK-LE-NEXT: mr r30, r1
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; CHECK-LE-NEXT: std r0, 16(r1)
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; CHECK-LE-NEXT: clrldi r0, r1, 59
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; CHECK-LE-NEXT: subfic r0, r0, -64
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; CHECK-LE-NEXT: stdux r1, r1, r0
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; CHECK-LE-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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; CHECK-LE-NEXT: addi r3, r3, .LCPI1_0@toc@l
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; CHECK-LE-NEXT: lxvd2x vs0, 0, r3
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; CHECK-LE-NEXT: addi r3, r1, 32
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; CHECK-LE-NEXT: stxvd2x vs0, 0, r3
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; CHECK-LE-NEXT: bl test1
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; CHECK-LE-NEXT: nop
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; CHECK-LE-NEXT: lwa r3, 32(r1)
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; CHECK-LE-NEXT: mr r1, r30
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; CHECK-LE-NEXT: ld r0, 16(r1)
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; CHECK-LE-NEXT: ld r30, -16(r1)
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; CHECK-LE-NEXT: mtlr r0
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_32byte_aligned_vector:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mflr r0
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; CHECK-BE-NEXT: std r30, -16(r1)
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; CHECK-BE-NEXT: std r0, 16(r1)
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; CHECK-BE-NEXT: clrldi r0, r1, 59
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; CHECK-BE-NEXT: mr r30, r1
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; CHECK-BE-NEXT: subfic r0, r0, -160
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; CHECK-BE-NEXT: stdux r1, r1, r0
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; CHECK-BE-NEXT: lis r3, -16384
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; CHECK-BE-NEXT: lis r4, -32768
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; CHECK-BE-NEXT: ori r3, r3, 1
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; CHECK-BE-NEXT: ori r4, r4, 1
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; CHECK-BE-NEXT: rldic r3, r3, 2, 30
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; CHECK-BE-NEXT: rldic r4, r4, 1, 31
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; CHECK-BE-NEXT: std r3, 136(r1)
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; CHECK-BE-NEXT: addi r3, r1, 128
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; CHECK-BE-NEXT: std r4, 128(r1)
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; CHECK-BE-NEXT: bl test1
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; CHECK-BE-NEXT: nop
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; CHECK-BE-NEXT: lwa r3, 128(r1)
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; CHECK-BE-NEXT: mr r1, r30
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; CHECK-BE-NEXT: ld r0, 16(r1)
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; CHECK-BE-NEXT: ld r30, -16(r1)
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; CHECK-BE-NEXT: mtlr r0
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; CHECK-BE-NEXT: blr
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entry:
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%a = alloca <4 x i32>, align 32
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%0 = bitcast <4 x i32>* %a to i8*
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call void @llvm.lifetime.start.p0i8(i64 16, i8* %0)
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store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* %a, align 32
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call void @test1(<4 x i32>* %a)
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%1 = load <4 x i32>, <4 x i32>* %a, align 32
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%vecext = extractelement <4 x i32> %1, i32 0
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%2 = bitcast <4 x i32>* %a to i8*
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call void @llvm.lifetime.end.p0i8(i64 16, i8* %2)
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ret i32 %vecext
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}
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@Arr1 = dso_local global [64 x i8] zeroinitializer, align 1
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define dso_local void @test_Array() nounwind {
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; CHECK-OPT-LABEL: @test_Array(
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; CHECK-OPT-NEXT: entry:
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; CHECK-OPT-NEXT: %Arr2 = alloca [64 x i16], align 2
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; CHECK-OPT: store <16 x i16> [[TMP0:%.*]], <16 x i16>* [[TMP0:%.*]], align 2
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; CHECK-LE-LABEL: test_Array:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mflr r0
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; CHECK-LE-NEXT: std r0, 16(r1)
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; CHECK-LE-NEXT: stdu r1, -176(r1)
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; CHECK-LE-NEXT: addis r4, r2, Arr1@toc@ha
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; CHECK-LE-NEXT: li r3, 0
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; CHECK-LE-NEXT: li r6, 65
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; CHECK-LE-NEXT: addi r5, r1, 46
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; CHECK-LE-NEXT: addi r4, r4, Arr1@toc@l
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; CHECK-LE-NEXT: stw r3, 44(r1)
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; CHECK-LE-NEXT: addi r4, r4, -1
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; CHECK-LE-NEXT: mtctr r6
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; CHECK-LE-NEXT: bdz .LBB2_2
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; CHECK-LE-NEXT: .p2align 5
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; CHECK-LE-NEXT: .LBB2_1: # %for.body
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; CHECK-LE-NEXT: #
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; CHECK-LE-NEXT: lbz r6, 1(r4)
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; CHECK-LE-NEXT: addi r7, r5, 2
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; CHECK-LE-NEXT: addi r4, r4, 1
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; CHECK-LE-NEXT: addi r3, r3, 1
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; CHECK-LE-NEXT: sth r6, 2(r5)
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; CHECK-LE-NEXT: mr r5, r7
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; CHECK-LE-NEXT: bdnz .LBB2_1
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; CHECK-LE-NEXT: .LBB2_2: # %for.cond.cleanup
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; CHECK-LE-NEXT: addi r3, r1, 48
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; CHECK-LE-NEXT: bl test_arr
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; CHECK-LE-NEXT: nop
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; CHECK-LE-NEXT: addi r1, r1, 176
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; CHECK-LE-NEXT: ld r0, 16(r1)
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; CHECK-LE-NEXT: mtlr r0
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_Array:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mflr r0
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; CHECK-BE-NEXT: std r0, 16(r1)
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; CHECK-BE-NEXT: stdu r1, -256(r1)
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; CHECK-BE-NEXT: addis r5, r2, Arr1@toc@ha
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; CHECK-BE-NEXT: li r3, 0
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; CHECK-BE-NEXT: addi r5, r5, Arr1@toc@l
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; CHECK-BE-NEXT: addi r4, r1, 126
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; CHECK-BE-NEXT: li r6, 65
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; CHECK-BE-NEXT: stw r3, 124(r1)
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; CHECK-BE-NEXT: addi r5, r5, -1
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; CHECK-BE-NEXT: mtctr r6
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; CHECK-BE-NEXT: bdz .LBB2_2
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; CHECK-BE-NEXT: .LBB2_1: # %for.body
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; CHECK-BE-NEXT: #
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; CHECK-BE-NEXT: lbz r6, 1(r5)
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; CHECK-BE-NEXT: addi r5, r5, 1
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; CHECK-BE-NEXT: addi r3, r3, 1
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; CHECK-BE-NEXT: sth r6, 2(r4)
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; CHECK-BE-NEXT: addi r4, r4, 2
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; CHECK-BE-NEXT: bdnz .LBB2_1
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; CHECK-BE-NEXT: .LBB2_2: # %for.cond.cleanup
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; CHECK-BE-NEXT: addi r3, r1, 128
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; CHECK-BE-NEXT: bl test_arr
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; CHECK-BE-NEXT: nop
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; CHECK-BE-NEXT: addi r1, r1, 256
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; CHECK-BE-NEXT: ld r0, 16(r1)
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; CHECK-BE-NEXT: mtlr r0
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; CHECK-BE-NEXT: blr
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entry:
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%Arr2 = alloca [64 x i16], align 2
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%i = alloca i32, align 4
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%0 = bitcast [64 x i16]* %Arr2 to i8*
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call void @llvm.lifetime.start.p0i8(i64 128, i8* %0)
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%1 = bitcast i32* %i to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* %1)
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store i32 0, i32* %i, align 4
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%2 = load i32, i32* %i, align 4
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%cmp = icmp slt i32 %2, 64
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond
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%3 = bitcast i32* %i to i8*
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call void @llvm.lifetime.end.p0i8(i64 4, i8* %3)
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br label %for.end
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for.body: ; preds = %for.cond
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%4 = load i32, i32* %i, align 4
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%idxprom = sext i32 %4 to i64
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%arrayidx = getelementptr inbounds [64 x i8], [64 x i8]* @Arr1, i64 0, i64 %idxprom
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%5 = load i8, i8* %arrayidx, align 1
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%conv = zext i8 %5 to i16
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%6 = load i32, i32* %i, align 4
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%idxprom1 = sext i32 %6 to i64
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%arrayidx2 = getelementptr inbounds [64 x i16], [64 x i16]* %Arr2, i64 0, i64 %idxprom1
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store i16 %conv, i16* %arrayidx2, align 2
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br label %for.inc
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for.inc: ; preds = %for.body
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%7 = load i32, i32* %i, align 4
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%inc = add nsw i32 %7, 1
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store i32 %inc, i32* %i, align 4
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br label %for.cond
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for.end: ; preds = %for.cond.cleanup
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%arraydecay = getelementptr inbounds [64 x i16], [64 x i16]* %Arr2, i64 0, i64 0
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call void @test_arr(i16* %arraydecay)
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%8 = bitcast [64 x i16]* %Arr2 to i8*
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call void @llvm.lifetime.end.p0i8(i64 128, i8* %8)
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ret void
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}
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declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) nounwind
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declare void @test(<8 x i32>*) nounwind
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declare void @test1(<4 x i32>*) nounwind
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declare void @test_arr(i16*)
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declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) nounwind
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