be7d425edc
This patch is the initial patch for support of the AIX extended vector ABI. The extended ABI treats vector registers V20-V31 as non-volatile and we add them as callee saved registers in this patch. Reviewed By: sfertile Differential Revision: https://reviews.llvm.org/D88676
39 lines
1.2 KiB
LLVM
39 lines
1.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
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; RUN: -data-sections=false < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
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; RUN: -data-sections=false < %s | FileCheck --check-prefix=CHECK64 %s
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@foo_ptr = global void (...)* @foo
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declare void @foo(...)
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@bar_ptr1 = global void (...)* bitcast (void ()* @bar to void (...)*)
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define void @bar() {
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entry:
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ret void
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}
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;CHECK: .csect .data[RW],2
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;CHECK-NEXT: .globl foo_ptr
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;CHECK-NEXT: .align 2
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;CHECK-NEXT: foo_ptr:
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;CHECK-NEXT: .vbyte 4, foo[DS]
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;CHECK-NEXT: .globl bar_ptr1
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;CHECK-NEXT: .align 2
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;CHECK-NEXT: bar_ptr1:
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;CHECK-NEXT: .vbyte 4, bar[DS]
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;CHECK-NEXT: .extern .foo[PR]
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;CHECK-NEXT: .extern foo[DS]
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;CHECK64: .csect .data[RW],3
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;CHECK64-NEXT: .globl foo_ptr
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;CHECK64-NEXT: .align 3
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;CHECK64-NEXT: foo_ptr:
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;CHECK64-NEXT: .vbyte 8, foo[DS]
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;CHECK64-NEXT: .globl bar_ptr1
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;CHECK64-NEXT: .align 3
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;CHECK64-NEXT: bar_ptr1:
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;CHECK64-NEXT: .vbyte 8, bar[DS]
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;CHECK64-NEXT: .extern .foo[PR]
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;CHECK64-NEXT: .extern foo[DS]
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