75117fb340
The zextload hook is only used to determine whether to insert a zero_extend or any_extend for narrow types leaving a basic block. Returning true from this hook tends to cause any load whose output leaves the basic block to become an LWU instead of an LW. Since we tend to prefer sexts for i32 compares on RV64, this can cause extra sext.w instructions to be created in other basic blocks. If we use LW instead of LWU this gives the MIR pass from D116397 a better chance of removing them. Another option might be to teach getPreferredExtendForValue in FunctionLoweringInfo.cpp about our preference for sign_extend of i32 compares. That would cause SIGN_EXTEND to be chosen for any value used by a compare instead of using the isZExtFree heuristic. That will require code to convert from the llvm::Type* to EVT/MVT as well as querying the type legalization actions to get the promoted type in order to call TargetLowering::isSExtCheaperThanZExt. That seemed like many extra steps when no other target wants it. Though it would avoid us needing to lean on the MIR pass in some cases. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D116567
293 lines
7.4 KiB
LLVM
293 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -no-integrated-as < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs -no-integrated-as < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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@gi = external global i32
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define i32 @constraint_r(i32 %a) nounwind {
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; RV32I-LABEL: constraint_r:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, %hi(gi)
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; RV32I-NEXT: lw a1, %lo(gi)(a1)
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; RV32I-NEXT: #APP
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_r:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, %hi(gi)
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; RV64I-NEXT: lw a1, %lo(gi)(a1)
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; RV64I-NEXT: #APP
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = load i32, i32* @gi
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%2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
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ret i32 %2
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}
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define i32 @constraint_i(i32 %a) nounwind {
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; RV32I-LABEL: constraint_i:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: addi a0, a0, 113
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_i:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: addi a0, a0, 113
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = load i32, i32* @gi
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%2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)
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ret i32 %2
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}
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define void @constraint_m(i32* %a) nounwind {
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; RV32I-LABEL: constraint_m:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_m:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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call void asm sideeffect "", "=*m"(i32* elementtype(i32) %a)
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ret void
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}
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define i32 @constraint_m2(i32* %a) nounwind {
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; RV32I-LABEL: constraint_m2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_m2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* elementtype(i32) %a)
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ret i32 %1
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}
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define void @constraint_I() nounwind {
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; RV32I-LABEL: constraint_I:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: #APP
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; RV32I-NEXT: addi a0, a0, -2048
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_I:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: addi a0, a0, 2047
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: #APP
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; RV64I-NEXT: addi a0, a0, -2048
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 2047)
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tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 -2048)
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ret void
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}
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define void @constraint_J() nounwind {
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; RV32I-LABEL: constraint_J:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: addi a0, a0, 0
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_J:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: addi a0, a0, 0
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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tail call void asm sideeffect "addi a0, a0, $0", "J"(i32 0)
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ret void
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}
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define void @constraint_K() nounwind {
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; RV32I-LABEL: constraint_K:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: csrwi mstatus, 31
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: #APP
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; RV32I-NEXT: csrwi mstatus, 0
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_K:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: csrwi mstatus, 31
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: #APP
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; RV64I-NEXT: csrwi mstatus, 0
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 31)
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tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 0)
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ret void
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}
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define void @constraint_A(i8* %a) nounwind {
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; RV32I-LABEL: constraint_A:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: sb s0, 0(a0)
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: #APP
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; RV32I-NEXT: lb s1, 0(a0)
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: constraint_A:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: sb s0, 0(a0)
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: #APP
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; RV64I-NEXT: lb s1, 0(a0)
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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tail call void asm sideeffect "sb s0, $0", "*A"(i8* elementtype(i8) %a)
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tail call void asm sideeffect "lb s1, $0", "*A"(i8* elementtype(i8) %a)
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ret void
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}
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define i32 @modifier_z_zero(i32 %a) nounwind {
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; RV32I-LABEL: modifier_z_zero:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: add a0, a0, zero
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: modifier_z_zero:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: add a0, a0, zero
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,i"(i32 %a, i32 0)
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ret i32 %1
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}
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define i32 @modifier_z_nonzero(i32 %a) nounwind {
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; RV32I-LABEL: modifier_z_nonzero:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: add a0, a0, 1
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: modifier_z_nonzero:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: add a0, a0, 1
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm "add $0, $1, ${2:z}", "=r,r,i"(i32 %a, i32 1)
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ret i32 %1
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}
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define i32 @modifier_i_imm(i32 %a) nounwind {
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; RV32I-LABEL: modifier_i_imm:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: addi a0, a0, 1
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: modifier_i_imm:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: addi a0, a0, 1
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 1)
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ret i32 %1
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}
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define i32 @modifier_i_reg(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: modifier_i_reg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: modifier_i_reg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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%1 = tail call i32 asm "add${2:i} $0, $1, $2", "=r,r,ri"(i32 %a, i32 %b)
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ret i32 %1
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}
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define void @operand_global() nounwind {
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; RV32I-LABEL: operand_global:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: .8byte gi
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: operand_global:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: .8byte gi
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: ret
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tail call void asm sideeffect ".8byte $0", "i"(i32* @gi)
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ret void
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}
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define void @operand_block_address() nounwind {
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; RV32I-LABEL: operand_block_address:
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; RV32I: # %bb.0:
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; RV32I-NEXT: #APP
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; RV32I-NEXT: j .Ltmp0
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; RV32I-NEXT: #NO_APP
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; RV32I-NEXT: .Ltmp0: # Block address taken
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; RV32I-NEXT: # %bb.1: # %bb
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: operand_block_address:
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; RV64I: # %bb.0:
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; RV64I-NEXT: #APP
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; RV64I-NEXT: j .Ltmp0
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; RV64I-NEXT: #NO_APP
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; RV64I-NEXT: .Ltmp0: # Block address taken
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; RV64I-NEXT: # %bb.1: # %bb
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; RV64I-NEXT: ret
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call void asm sideeffect "j $0", "i"(i8* blockaddress(@operand_block_address, %bb))
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br label %bb
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bb:
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ret void
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}
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; TODO: expand tests for more complex constraints, out of range immediates etc
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