3d869c88bb
Make sure that we really don't emit quad-precision unless the "hard-quad-float" feature is available. Add missing replacement instruction patterns that are needed to emit alternative code for conditional moves of quad-precision floats. Test from koakuma. Reviewed By: koakuma Differential Revision: https://reviews.llvm.org/D119104
39 lines
1.2 KiB
LLVM
39 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC64
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define fp128 @fpselect_softfloat(i32 signext %0, fp128 %1, fp128 %2) #0 {
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; SPARC64-LABEL: fpselect_softfloat:
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; SPARC64: .cfi_startproc
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; SPARC64-NEXT: ! %bb.0:
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; SPARC64-NEXT: cmp %o0, 0
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; SPARC64-NEXT: fmovd %f8, %f0
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; SPARC64-NEXT: fmovd %f10, %f2
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; SPARC64-NEXT: be .LBB0_2
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; SPARC64-NEXT: nop
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; SPARC64-NEXT: ! %bb.1:
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; SPARC64-NEXT: fmovd %f4, %f0
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; SPARC64-NEXT: fmovd %f6, %f2
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; SPARC64-NEXT: .LBB0_2:
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; SPARC64-NEXT: retl
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; SPARC64-NEXT: nop
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%a = icmp eq i32 %0, 0
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%b = select i1 %a, fp128 %2, fp128 %1
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ret fp128 %b
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}
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define fp128 @fpselect_hardfloat(i32 signext %0, fp128 %1, fp128 %2) #1 {
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; SPARC64-LABEL: fpselect_hardfloat:
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; SPARC64: .cfi_startproc
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; SPARC64-NEXT: ! %bb.0:
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; SPARC64-NEXT: fmovq %f4, %f0
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; SPARC64-NEXT: cmp %o0, 0
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; SPARC64-NEXT: retl
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; SPARC64-NEXT: fmovqe %icc, %f8, %f0
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%a = icmp eq i32 %0, 0
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%b = select i1 %a, fp128 %2, fp128 %1
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ret fp128 %b
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}
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attributes #0 = { "target-features"="-hard-quad-float" }
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attributes #1 = { "target-features"="+hard-quad-float" }
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