4ce26deac2
We already have reassociation code for Adds and Ors separately in DAG combiner, this adds it for the combination of the two where Ors act like Adds. It reassociates (add (or (x, c), y) -> (add (add (x, y), c)) where we know that the Ors operands have no common bits set, and the Or has one use. Differential Revision: https://reviews.llvm.org/D104765
117 lines
3.2 KiB
LLVM
117 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Test selection of addresses with indices in cases where the address
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; is used once.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; A simple index address.
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define void @f1(i64 %addr, i64 %index) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lb %r0, 0(%r3,%r2)
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; CHECK-NEXT: br %r14
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%add = add i64 %addr, %index
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%ptr = inttoptr i64 %add to i8 *
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%a = load volatile i8, i8 *%ptr
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ret void
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}
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; An address with an index and a displacement (order 1).
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define void @f2(i64 %addr, i64 %index) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lb %r0, 100(%r3,%r2)
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; CHECK-NEXT: br %r14
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%add1 = add i64 %addr, %index
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%add2 = add i64 %add1, 100
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%ptr = inttoptr i64 %add2 to i8 *
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%a = load volatile i8, i8 *%ptr
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ret void
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}
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; An address with an index and a displacement (order 2).
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define void @f3(i64 %addr, i64 %index) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lb %r0, 100(%r3,%r2)
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; CHECK-NEXT: br %r14
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%add1 = add i64 %addr, 100
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%add2 = add i64 %add1, %index
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%ptr = inttoptr i64 %add2 to i8 *
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%a = load volatile i8, i8 *%ptr
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ret void
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}
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; An address with an index and a subtracted displacement (order 1).
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define void @f4(i64 %addr, i64 %index) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lb %r0, -100(%r3,%r2)
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; CHECK-NEXT: br %r14
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%add1 = add i64 %addr, %index
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%add2 = sub i64 %add1, 100
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%ptr = inttoptr i64 %add2 to i8 *
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%a = load volatile i8, i8 *%ptr
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ret void
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}
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; An address with an index and a subtracted displacement (order 2).
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define void @f5(i64 %addr, i64 %index) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lb %r0, -100(%r3,%r2)
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; CHECK-NEXT: br %r14
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%add1 = sub i64 %addr, 100
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%add2 = add i64 %add1, %index
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%ptr = inttoptr i64 %add2 to i8 *
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%a = load volatile i8, i8 *%ptr
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ret void
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}
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; An address with an index and a displacement added using OR.
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define void @f6(i64 %addr, i64 %index) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nill %r2, 65528
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; CHECK-NEXT: lb %r0, 6(%r2,%r3)
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; CHECK-NEXT: br %r14
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%aligned = and i64 %addr, -8
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%or = or i64 %aligned, 6
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%add = add i64 %or, %index
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%ptr = inttoptr i64 %add to i8 *
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%a = load volatile i8, i8 *%ptr
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ret void
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}
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; Like f6, but without the masking. This OR doesn't count as a displacement.
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define void @f7(i64 %addr, i64 %index) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: oill %r2, 6
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; CHECK-NEXT: lb %r0, 0(%r3,%r2)
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; CHECK-NEXT: br %r14
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%or = or i64 %addr, 6
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%add = add i64 %or, %index
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%ptr = inttoptr i64 %add to i8 *
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%a = load volatile i8, i8 *%ptr
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ret void
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}
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; Like f6, but with the OR applied after the index. We don't know anything
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; about the alignment of %add here.
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define void @f8(i64 %addr, i64 %index) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nill %r2, 65528
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; CHECK-NEXT: agr %r2, %r3
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; CHECK-NEXT: oill %r2, 6
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; CHECK-NEXT: lb %r0, 0(%r2)
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; CHECK-NEXT: br %r14
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%aligned = and i64 %addr, -8
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%add = add i64 %aligned, %index
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%or = or i64 %add, 6
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%ptr = inttoptr i64 %or to i8 *
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%a = load volatile i8, i8 *%ptr
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ret void
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}
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