d3b33a7810
Claim to not have any vector support to dissuade SLP, LV and friends from generating SIMD IR for the VE target. We will take this back once vector isel is stable. Reviewed By: kaz7, fhahn Differential Revision: https://reviews.llvm.org/D90462
39 lines
1.7 KiB
LLVM
39 lines
1.7 KiB
LLVM
; RUN: opt < %s -loop-vectorize -mtriple=ve-linux -S | FileCheck %s -check-prefix=VE
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; RUN: opt < %s -loop-vectorize -mtriple=x86_64-pc_linux -mcpu=core-avx2 -S | FileCheck %s -check-prefix=AVX
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; Make sure LV does not trigger for VE on an appealing loop that vectorizes for x86 AVX.
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; TODO: Remove this test once VE vector isel is deemed stable.
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; VE-NOT: llvm.loop.isvectorized
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; AVX: llvm.loop.isvectorized
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define dso_local void @foo(i32* noalias nocapture %A, i32* noalias nocapture readonly %B, i32 signext %n) local_unnamed_addr {
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entry:
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%cmp = icmp sgt i32 %n, 0
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br i1 %cmp, label %omp.inner.for.body.preheader, label %simd.if.end
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omp.inner.for.body.preheader: ; preds = %entry
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%wide.trip.count = zext i32 %n to i64
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br label %omp.inner.for.body
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omp.inner.for.body: ; preds = %omp.inner.for.body.preheader, %omp.inner.for.body
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%indvars.iv = phi i64 [ 0, %omp.inner.for.body.preheader ], [ %indvars.iv.next, %omp.inner.for.body ]
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%arrayidx = getelementptr inbounds i32, i32* %B, i64 %indvars.iv
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%0 = load i32, i32* %arrayidx, align 4, !llvm.access.group !6
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%mul6 = mul nsw i32 %0, 3
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%arrayidx8 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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store i32 %mul6, i32* %arrayidx8, align 4, !llvm.access.group !6
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond.not, label %simd.if.end, label %omp.inner.for.body, !llvm.loop !7
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simd.if.end: ; preds = %omp.inner.for.body, %entry
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ret void
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}
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!6 = distinct !{}
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!7 = distinct !{!7, !8, !9}
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!8 = !{!"llvm.loop.parallel_accesses", !6}
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!9 = !{!"llvm.loop.vectorize.enable", i1 true}
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