2ac5ebedea
SLP vectorizer emits extracts for externally used vectorized scalars and estimates the cost for each such extract. But in many cases these scalars are input for insertelement instructions, forming buildvector, and instead of extractelement/insertelement pair we can emit/cost estimate shuffle(s) cost and generate series of shuffles, which can be further optimized. Tested using test-suite (+SPEC2017), the tests passed, SLP was able to generate/vectorize more instructions in many cases and it allowed to reduce number of re-vectorization attempts (where we could try to vectorize buildector insertelements again and again). Differential Revision: https://reviews.llvm.org/D107966
70 lines
3.5 KiB
LLVM
70 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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;RUN: opt -S -slp-vectorizer -mtriple=x86_64-unknown-linux-android23 < %s | FileCheck %s
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define void @test() {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr undef, i32 2
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; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr undef, align 4
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; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x float> [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i32 1
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; CHECK-NEXT: [[TMP7:%.*]] = fcmp olt float [[TMP6]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = insertelement <2 x float> zeroinitializer, float 0.000000e+00, i64 0
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; CHECK-NEXT: store <2 x float> zeroinitializer, ptr null, align 4
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; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP2]], <2 x i32> <i32 3, i32 1>
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; CHECK-NEXT: store <2 x float> zeroinitializer, ptr null, align 4
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; CHECK-NEXT: ret void
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;
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%1 = getelementptr inbounds float, ptr undef, i32 2
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%2 = load float, ptr %1, align 4
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%3 = load float, ptr undef, align 4
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%4 = fsub float %2, %3
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%5 = getelementptr inbounds float, ptr undef, i32 3
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%6 = load float, ptr %5, align 4
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%7 = getelementptr inbounds float, ptr undef, i32 1
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%8 = load float, ptr %7, align 4
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%9 = fsub float %6, %8
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%10 = fcmp olt float %9, %4
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%11 = insertelement <2 x float> undef, float %3, i64 0
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%12 = insertelement <2 x float> zeroinitializer, float 0.000000e+00, i64 0
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store <2 x float> zeroinitializer, ptr null, align 4
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%13 = insertelement <2 x float> %11, float %6, i64 0
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store <2 x float> zeroinitializer, ptr null, align 4
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ret void
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}
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define void @test1() {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr undef, i32 2
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; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr undef, align 4
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; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x float> [[TMP2]], [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP4]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x float> [[TMP4]], i32 1
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; CHECK-NEXT: [[TMP7:%.*]] = fcmp olt float [[TMP6]], [[TMP5]]
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; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <2 x i32> <i32 0, i32 1>
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; CHECK-NEXT: store <2 x float> [[TMP8]], ptr null, align 4
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; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP2]], <2 x i32> <i32 0, i32 3>
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; CHECK-NEXT: store <2 x float> [[TMP9]], ptr null, align 4
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; CHECK-NEXT: ret void
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;
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%1 = getelementptr inbounds float, ptr undef, i32 2
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%2 = load float, ptr %1, align 4
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%3 = load float, ptr undef, align 4
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%4 = fsub float %2, %3
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%5 = getelementptr inbounds float, ptr undef, i32 3
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%6 = load float, ptr %5, align 4
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%7 = getelementptr inbounds float, ptr undef, i32 1
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%8 = load float, ptr %7, align 4
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%9 = fsub float %6, %8
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%10 = fcmp olt float %9, %4
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%.sroa.0.0.vec.insert.i5.i10 = insertelement <2 x float> undef, float %3, i64 0
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%.sroa.0.4.vec.insert.i10.i13 = insertelement <2 x float> %.sroa.0.0.vec.insert.i5.i10, float %8, i64 1
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store <2 x float> %.sroa.0.4.vec.insert.i10.i13, ptr null, align 4
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%.sroa.0.4.vec.insert.i10.i13.2 = insertelement <2 x float> %.sroa.0.0.vec.insert.i5.i10, float %6, i64 1
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store <2 x float> %.sroa.0.4.vec.insert.i10.i13.2, ptr null, align 4
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ret void
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}
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