Files
clang-p2996/mlir/test/Target/LLVMIR/data-layout.mlir
Alex Zinenko eb27da7dec [mlir] Ignore index data layout in translation to LLVM
It can be present, but is irrelevant for the translation.
2022-03-02 16:56:21 +01:00

38 lines
1.0 KiB
MLIR

// RUN: mlir-translate -mlir-to-llvmir %s -split-input-file -verify-diagnostics | FileCheck %s
// CHECK: target datalayout
// CHECK: E-
// CHECK: i64:64:128
// CHECK: f80:128:256
module attributes {dlti.dl_spec = #dlti.dl_spec<
#dlti.dl_entry<"dlti.endianness", "big">,
#dlti.dl_entry<index, 64>,
#dlti.dl_entry<i64, dense<[64,128]> : vector<2xi32>>,
#dlti.dl_entry<f80, dense<[128,256]> : vector<2xi32>>
>} {
llvm.func @foo() {
llvm.return
}
}
// -----
// expected-error@below {{unsupported data layout for non-signless integer 'ui64'}}
module attributes {dlti.dl_spec = #dlti.dl_spec<
#dlti.dl_entry<ui64, dense<[64,128]> : vector<2xi32>>>
} {}
// -----
// expected-error@below {{unsupported type in data layout: 'bf16'}}
module attributes {dlti.dl_spec = #dlti.dl_spec<
#dlti.dl_entry<bf16, dense<[64,128]> : vector<2xi32>>>
} {}
// -----
// expected-error@below {{unsupported data layout key "foo"}}
module attributes {dlti.dl_spec = #dlti.dl_spec<
#dlti.dl_entry<"foo", dense<[64,128]> : vector<2xi32>>>
} {}