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clang-p2996/llvm/test/CodeGen/AMDGPU/GlobalISel
History
Matt Arsenault 99c7e918b5 GlobalISel: Use LLT in call lowering callbacks 
This preserves the memory type so the lowerings can rely on them.
2021-07-01 12:15:54 -04:00
..
add_shl.ll
[AMDGPU] Make some VOP3 insts commutable
2021-04-28 13:59:08 -04:00
add.v2i16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
amdgpu-irtranslator.ll
…
andn2.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
artifact-combiner-anyext.mir
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artifact-combiner-build-vector.mir
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artifact-combiner-concat-vectors.mir
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artifact-combiner-extract.mir
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artifact-combiner-sext.mir
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artifact-combiner-trunc.mir
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artifact-combiner-unmerge-values.mir
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artifact-combiner-zext.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ashr.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
atomic_optimizations_mul_one.ll
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bool-legalization.ll
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bswap.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
combine-add-nullptr.mir
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combine-add-to-ptradd.mir
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combine-amdgpu-cvt-f32-ubyte.mir
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combine-ashr-narrow.mir
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combine-ext-legalizer.mir
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combine-fcanonicalize.mir
AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZE
2021-04-27 12:26:37 +02:00
combine-itofp.mir
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combine-lshr-narrow.mir
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combine-or-redundant.mir
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combine-redundant-and.mir
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combine-sext-inreg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
combine-shift-imm-chain-illegal-types.mir
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combine-shift-imm-chain-shlsat.mir
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combine-shift-imm-chain.ll
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combine-shift-of-shifted-logic-shlsat.mir
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combine-shift-of-shifted-logic.ll
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combine-shl-from-extend-narrow.postlegal.mir
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combine-shl-from-extend-narrow.prelegal.mir
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combine-shl-narrow.mir
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combine-short-clamp.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
combine-trunc-shl.mir
…
combine-urem-pow-2.mir
GlobalISel: Handle G_BUILD_VECTOR in isKnownToBeAPowerOfTwo
2021-03-22 14:20:35 -04:00
combine-zext-trunc.mir
Reland [GlobalISel] Combine zext(trunc x) to x
2021-03-05 11:05:37 +01:00
constant-bus-restriction.ll
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cvt_f32_ubyte.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
divergent-control-flow.ll
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect
2021-03-05 11:05:37 +01:00
dummy-target.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
dynamic-alloca-divergent.ll
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dynamic-alloca-uniform.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
extractelement-stack-lower.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
extractelement.i8.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
extractelement.i16.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
extractelement.i128.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
extractelement.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
fdiv.f16.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
fdiv.f32.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
fdiv.f64.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
flat-scratch-init.ll
[AMDGPU] Add support for architected flat scratch
2021-05-14 10:53:48 -07:00
flat-scratch.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
floor.f64.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
fma.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
fmax_legacy.ll
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fmed3.ll
AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZE
2021-04-27 12:26:37 +02:00
fmin_legacy.ll
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fmul.v2f16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
fp64-atomics-gfx90a.ll
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fpow.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
frem.ll
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
fshl.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
fshr.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
function-returns.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
global-value.illegal.ll
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global-value.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
hip.extern.shared.array.ll
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image_ls_mipmap_zero.a16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
image_ls_mipmap_zero.ll
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inline-asm.ll
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insertelement-stack-lower.ll
AMDGPU/GlobalISel: Improve private addressing mode matching
2021-03-11 10:23:35 -05:00
insertelement.i8.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
insertelement.i16.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
insertelement.large.ll
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
2021-04-01 14:21:00 +03:00
insertelement.ll
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
2021-06-24 12:41:22 +09:00
inst-select-abs.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-add.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-add.s16.mir
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inst-select-amdgcn.class.mir
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inst-select-amdgcn.class.s16.mir
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inst-select-amdgcn.cos.mir
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inst-select-amdgcn.cos.s16.mir
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inst-select-amdgcn.cvt.pk.i16.mir
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inst-select-amdgcn.cvt.pk.u16.mir
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inst-select-amdgcn.cvt.pknorm.i16.mir
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inst-select-amdgcn.cvt.pknorm.u16.mir
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inst-select-amdgcn.cvt.pkrtz.mir
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inst-select-amdgcn.ds.swizzle.mir
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inst-select-amdgcn.exp.mir
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inst-select-amdgcn.fmad.ftz.mir
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inst-select-amdgcn.fmed3.mir
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inst-select-amdgcn.fmed3.s16.mir
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inst-select-amdgcn.fract.mir
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inst-select-amdgcn.fract.s16.mir
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inst-select-amdgcn.groupstaticsize.mir
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inst-select-amdgcn.ldexp.mir
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inst-select-amdgcn.ldexp.s16.mir
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inst-select-amdgcn.mbcnt.lo.mir
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inst-select-amdgcn.mul.u24.mir
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inst-select-amdgcn.rcp.legacy.mir
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inst-select-amdgcn.rcp.mir
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inst-select-amdgcn.rcp.s16.mir
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inst-select-amdgcn.readfirstlane.mir
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inst-select-amdgcn.reloc.constant.mir
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inst-select-amdgcn.rsq.clamp.mir
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inst-select-amdgcn.rsq.legacy.mir
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inst-select-amdgcn.rsq.mir
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inst-select-amdgcn.rsq.s16.mir
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inst-select-amdgcn.s.barrier.mir
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inst-select-amdgcn.s.sendmsg.mir
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inst-select-amdgcn.sffbh.mir
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inst-select-amdgcn.sin.mir
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inst-select-amdgcn.sin.s16.mir
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inst-select-amdgpu-atomic-cmpxchg-flat.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-amdgpu-atomic-cmpxchg-global.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-amdgpu-ffbh-u32.mir
…
inst-select-and.mir
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inst-select-anyext.mir
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inst-select-ashr.mir
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inst-select-ashr.s16.mir
…
inst-select-ashr.v2s16.mir
…
inst-select-atomic-cmpxchg-local.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-atomic-cmpxchg-region.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-atomicrmw-add-flat.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-atomicrmw-add-global.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-atomicrmw-fadd-local.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-atomicrmw-fadd-region.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-atomicrmw-xchg-local.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-atomicrmw-xchg-region.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-bitcast.mir
…
inst-select-bitreverse.mir
[AMDGPU] Better codegen for i64 bitreverse
2021-02-26 15:51:36 +00:00
inst-select-br.mir
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inst-select-brcond.mir
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inst-select-bswap.mir
…
inst-select-build-vector-trunc.v2s16.mir
…
inst-select-build-vector.mir
…
inst-select-concat-vectors.mir
…
inst-select-constant.mir
…
inst-select-copy.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-ctlz-zero-undef.mir
…
inst-select-ctpop.mir
…
inst-select-cttz-zero-undef.mir
…
inst-select-extract-vector-elt.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-extract.mir
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inst-select-fabs.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fadd.s16.mir
…
inst-select-fadd.s32.mir
…
inst-select-fadd.s64.mir
…
inst-select-fcanonicalize.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fceil.mir
…
inst-select-fceil.s16.mir
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inst-select-fcmp.mir
…
inst-select-fcmp.s16.mir
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inst-select-fconstant.mir
…
inst-select-fexp2.mir
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inst-select-ffloor.s16.mir
…
inst-select-ffloor.s32.mir
…
inst-select-ffloor.s64.mir
…
inst-select-fma.s32.mir
…
inst-select-fmad.s32.mir
…
inst-select-fmaxnum-ieee.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-fmaxnum-ieee.s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fmaxnum-ieee.v2s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fmaxnum.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-fmaxnum.s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fmaxnum.v2s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fminnum-ieee.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-fminnum-ieee.s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fminnum-ieee.v2s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fminnum.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-fminnum.s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fminnum.v2s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fmul.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-fmul.v2s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fneg.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-fptosi.mir
…
inst-select-fptoui.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-fract.f64.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-frame-index.mir
…
inst-select-freeze.mir
…
inst-select-frint.mir
…
inst-select-frint.s16.mir
…
inst-select-fshr.mir
…
inst-select-icmp.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-icmp.s16.mir
…
inst-select-icmp.s64.mir
…
inst-select-implicit-def.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-insert-vector-elt.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-insert.mir
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks
2021-04-30 14:10:50 +01:00
inst-select-insert.xfail.mir
…
inst-select-intrinsic-trunc.mir
…
inst-select-intrinsic-trunc.s16.mir
…
inst-select-inttoptr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-atomic-flat.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-atomic-global.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-atomic-local.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-constant.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-flat.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-global-saddr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-global.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-global.s96.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-local-128.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-local.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-private.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-smrd.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-lshr.mir
…
inst-select-lshr.s16.mir
…
inst-select-lshr.v2s16.mir
…
inst-select-merge-values.mir
…
inst-select-mul.mir
…
inst-select-or.mir
…
inst-select-pattern-add3.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-pattern-and-or.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-pattern-or3.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-pattern-smed3.mir
…
inst-select-pattern-smed3.s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-pattern-umed3.mir
…
inst-select-pattern-umed3.s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-pattern-xor3.mir
…
inst-select-phi.mir
…
inst-select-ptr-add.mir
…
inst-select-ptrmask.mir
…
inst-select-ptrtoint.mir
…
inst-select-returnaddress.mir
…
inst-select-sbfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
inst-select-scalar-packed.xfail.mir
…
inst-select-select.mir
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inst-select-sext-inreg.mir
…
inst-select-sext.mir
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inst-select-shl.mir
…
inst-select-shl.s16.mir
…
inst-select-shl.v2s16.mir
…
inst-select-shuffle-vector.v2s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-sitofp.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-smax.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-smin.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-smulh.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-store-atomic-flat.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-store-atomic-local.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-store-flat.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-store-global.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-store-global.s96.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-store-local.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-store-private.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-sub.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-trunc.mir
…
inst-select-trunc.v2s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-uadde.gfx10.mir
…
inst-select-uadde.mir
…
inst-select-uaddo.mir
…
inst-select-ubfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
inst-select-uitofp.mir
…
inst-select-umax.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-umin.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-umulh.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
inst-select-unmerge-values.mir
…
inst-select-usube.gfx10.mir
…
inst-select-usube.mir
…
inst-select-usubo.mir
…
inst-select-xor.mir
…
inst-select-zext.mir
…
irtranslator-amdgcn-sendmsg.ll
…
irtranslator-amdgpu_kernel-system-sgprs.ll
…
irtranslator-amdgpu_kernel.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-amdgpu_ps.ll
…
irtranslator-amdgpu_vs.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-atomicrmw.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-call-implicit-args.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-call-non-fixed.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-call-return-values.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-call-sret.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-call.ll
GlobalISel: Use LLT in call lowering callbacks
2021-07-01 12:15:54 -04:00
irtranslator-constantexpr.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-constrained-fp.ll
…
irtranslator-fast-math-flags.ll
…
irtranslator-fence.ll
…
irtranslator-fixed-function-abi-vgpr-args.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-function-args.ll
GlobalISel: Use LLT in call lowering callbacks
2021-07-01 12:15:54 -04:00
irtranslator-getelementptr.ll
…
irtranslator-indirect-call.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-inline-asm.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-memory-intrinsics.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-metadata.ll
…
irtranslator-ptrmask.ll
…
irtranslator-readnone-intrinsic-callsite.ll
…
irtranslator-sat.ll
…
irtranslator-sibling-call.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-struct-return-intrinsics.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-tail-call.ll
AMDGPU/GlobalISel: Implement tail calls
2021-05-13 18:57:42 -04:00
lds-global-non-entry-func.ll
[AMDGPU] Rename "LDS lowering" pass name.
2021-04-14 20:19:53 +05:30
lds-global-value.ll
[AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering.
2021-06-07 18:00:41 +05:30
lds-misaligned-bug.ll
[AMDGPU] Only use ds_read/write_b128 for alignment >= 16
2021-04-08 08:12:05 +05:30
lds-relocs.ll
[AMDGPU] Lower kernel LDS into a sorted structure
2021-05-25 11:29:29 -07:00
lds-size.ll
…
lds-zero-initializer.ll
…
legalize-add.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-addrspacecast.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-amdgcn.if-invalid.mir
…
legalize-amdgcn.if.xfail.mir
…
legalize-amdgcn.rsq.clamp.mir
…
legalize-amdgcn.wavefrontsize.mir
…
legalize-and.mir
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
legalize-anyext.mir
…
legalize-ashr.mir
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
legalize-atomic-cmpxchg-with-success.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomic-cmpxchg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-add.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-and.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-fadd-global.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-fadd-local.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-max.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-min.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-nand.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-or.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-sub.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-umax.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-umin.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-xchg-flat.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-xchg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-xor.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-bitcast.mir
…
legalize-bitreverse.mir
[AMDGPU] Better codegen for i64 bitreverse
2021-02-26 15:51:36 +00:00
legalize-block-addr.mir
…
legalize-brcond.mir
…
legalize-bswap.mir
…
legalize-build-vector-trunc.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-build-vector.mir
…
legalize-build-vector.s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-concat-vectors.mir
…
legalize-constant.mir
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
legalize-ctlz-zero-undef.mir
…
legalize-ctlz.mir
…
legalize-ctpop.mir
…
legalize-cttz-zero-undef.mir
…
legalize-cttz.mir
…
legalize-extract-vector-elt.mir
GlobalISel: Preserve memory type when reducing load/store width
2021-06-30 17:05:29 -04:00
legalize-extract.mir
…
legalize-fabs.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fadd.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fcanonicalize.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fceil.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fcmp.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-fconstant.mir
…
legalize-fcopysign.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fcos.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fdiv.mir
…
legalize-fexp2.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fexp.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-ffloor.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-flog2.mir
…
legalize-flog10.mir
…
legalize-flog.mir
…
legalize-fma.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fmad.s16.mir
…
legalize-fmad.s32.mir
…
legalize-fmad.s64.mir
…
legalize-fmaxnum.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fminnum.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fmul.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fneg.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fpext.mir
…
legalize-fpow.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fpowi.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fptosi.mir
[amdgpu] Improve the from f32 to i64.
2021-06-19 12:46:48 -04:00
legalize-fptoui.mir
[amdgpu] Improve the from f32 to i64.
2021-06-19 12:46:48 -04:00
legalize-fptrunc.mir
…
legalize-freeze.mir
…
legalize-frint.mir
…
legalize-fshl.mir
GlobalISel: Lower funnel shifts
2021-03-23 09:11:17 -04:00
legalize-fshr.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fsin.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fsqrt.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-fsub.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-icmp.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-implicit-def-s1025.mir
…
legalize-implicit-def.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-insert-vector-elt.mir
GlobalISel: Preserve memory type when reducing load/store width
2021-06-30 17:05:29 -04:00
legalize-insert.mir
…
legalize-intrinsic-amdgcn-fdiv-fast.mir
…
legalize-intrinsic-round.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-intrinsic-trunc.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-inttoptr.mir
…
legalize-jump-table.mir
…
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-llvm.amdgcn.image.dim.a16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-llvm.amdgcn.image.load.2d.d16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-llvm.amdgcn.image.load.2d.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-llvm.amdgcn.image.load.3d.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-llvm.amdgcn.image.sample.a16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-llvm.amdgcn.image.sample.g16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-llvm.amdgcn.image.store.2d.d16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-llvm.amdgcn.s.buffer.load.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-load-constant-32bit.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-load-constant.mir
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
legalize-load-flat.mir
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
legalize-load-global.mir
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
legalize-load-local.mir
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
legalize-load-memory-metadata.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-load-private.mir
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
legalize-lshr.mir
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
legalize-merge-values-build-vector.mir
…
legalize-merge-values.mir
…
legalize-mul.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-or.mir
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
legalize-phi.mir
…
legalize-ptr-add.mir
…
legalize-ptrmask.mir
…
legalize-ptrtoint.mir
…
legalize-sadde.mir
…
legalize-saddo.mir
…
legalize-saddsat.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-sbfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
legalize-sdiv.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-select.mir
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
legalize-sext-inreg.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-sext.mir
…
legalize-sextload-constant-32bit.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-sextload-flat.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-sextload-global.mir
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
legalize-sextload-local.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-sextload-private.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-shl.mir
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
legalize-shuffle-vector.mir
…
legalize-shuffle-vector.s16.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-sitofp.mir
…
legalize-smax.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-smin.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-smulh.mir
…
legalize-smulo.mir
[GlobalISel][AMDGPU] Lower G_UMULO/G_SMULO
2021-03-23 05:45:43 +00:00
legalize-srem.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-sshlsat.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-ssube.mir
…
legalize-ssubo.mir
…
legalize-ssubsat.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-store-global.mir
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
legalize-store.mir
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
legalize-sub.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-trunc.mir
…
legalize-uadde.mir
…
legalize-uaddo.mir
…
legalize-uaddsat.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-ubfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
legalize-udiv.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-uitofp.mir
…
legalize-umax.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-umin.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-umulh.mir
…
legalize-umulo.mir
[GlobalISel][AMDGPU] Lower G_UMULO/G_SMULO
2021-03-23 05:45:43 +00:00
legalize-unmerge-values.mir
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks
2021-04-30 14:10:50 +01:00
legalize-urem.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-ushlsat.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-usube.mir
…
legalize-usubo.mir
…
legalize-usubsat.mir
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
legalize-xor.mir
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
legalize-zext.mir
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
legalize-zextload-constant-32bit.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-zextload-flat.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-zextload-global.mir
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
legalize-zextload-local.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-zextload-private.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.abs.ll
[AMDGPU][GlobalISel] Legalize G_ABS
2021-06-04 14:46:43 +02:00
llvm.amdgcn.atomic.dec.ll
…
llvm.amdgcn.atomic.inc.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.ballot.i32.ll
…
llvm.amdgcn.ballot.i64.ll
…
llvm.amdgcn.dispatch.id.ll
…
llvm.amdgcn.dispatch.ptr.ll
…
llvm.amdgcn.div.fmas.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
llvm.amdgcn.div.scale.ll
…
llvm.amdgcn.ds.append.ll
…
llvm.amdgcn.ds.consume.ll
…
llvm.amdgcn.ds.fadd.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
llvm.amdgcn.ds.fmax.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.ds.fmin.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
llvm.amdgcn.ds.gws.barrier.ll
…
llvm.amdgcn.ds.gws.init.ll
…
llvm.amdgcn.ds.gws.sema.br.ll
…
llvm.amdgcn.ds.gws.sema.release.all.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.ds.gws.sema.v.ll
…
llvm.amdgcn.ds.ordered.add.gfx10.ll
…
llvm.amdgcn.ds.ordered.add.ll
…
llvm.amdgcn.ds.ordered.swap.ll
…
llvm.amdgcn.end.cf.i32.ll
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect
2021-03-05 11:05:37 +01:00
llvm.amdgcn.end.cf.i64.ll
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect
2021-03-05 11:05:37 +01:00
llvm.amdgcn.fdot2.ll
…
llvm.amdgcn.fmul.legacy.ll
…
llvm.amdgcn.global.atomic.csub.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
llvm.amdgcn.global.atomic.fadd-with-ret.ll
…
llvm.amdgcn.global.atomic.fadd.ll
…
llvm.amdgcn.icmp.ll
…
llvm.amdgcn.if.break.i32.ll
…
llvm.amdgcn.if.break.i64.ll
…
llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU] Make some VOP3 insts commutable
2021-04-28 13:59:08 -04:00
llvm.amdgcn.image.atomic.dim.ll
AMDGPU/GlobalISel: Fix selection of image intrinsics with unused return
2021-04-29 20:56:03 +02:00
llvm.amdgcn.image.atomic.dim.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Make some VOP3 insts commutable
2021-04-28 13:59:08 -04:00
llvm.amdgcn.image.gather4.dim.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.gather4.o.dim.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.getresinfo.a16.ll
…
llvm.amdgcn.image.getresinfo.ll
…
llvm.amdgcn.image.load.1d.d16.ll
…
llvm.amdgcn.image.load.1d.ll
[AMDGPU] Add some image tests with enable-prt-strict-null disabled. NFC.
2021-03-31 17:27:20 +01:00
llvm.amdgcn.image.load.2d.ll
…
llvm.amdgcn.image.load.2darraymsaa.a16.ll
…
llvm.amdgcn.image.load.2darraymsaa.ll
…
llvm.amdgcn.image.load.3d.a16.ll
…
llvm.amdgcn.image.load.3d.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.image.sample.g16.ll
[AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
2021-06-08 11:11:40 +09:00
llvm.amdgcn.image.sample.ltolz.a16.ll
[AMDGPU] Make some VOP3 insts commutable
2021-04-28 13:59:08 -04:00
llvm.amdgcn.image.sample.ltolz.ll
…
llvm.amdgcn.image.store.2d.d16.ll
…
llvm.amdgcn.image.store.2d.ll
…
llvm.amdgcn.implicit.buffer.ptr.ll
…
llvm.amdgcn.init.exec.ll
…
llvm.amdgcn.init.exec.wave32.ll
…
llvm.amdgcn.interp.p1.f16.ll
…
llvm.amdgcn.intersect_ray.ll
Reland "[AMDGPU] Add gfx1013 target"
2021-06-08 21:15:35 -04:00
llvm.amdgcn.is.private.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
llvm.amdgcn.is.shared.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
llvm.amdgcn.kernarg.segment.ptr.ll
…
llvm.amdgcn.mov.dpp8.ll
…
llvm.amdgcn.mov.dpp.ll
…
llvm.amdgcn.permlane.ll
…
llvm.amdgcn.queue.ptr.ll
…
llvm.amdgcn.raw.buffer.atomic.add.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
…
llvm.amdgcn.raw.buffer.atomic.fadd.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.buffer.load.format.f16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.buffer.load.format.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.buffer.load.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.buffer.store.format.f16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.buffer.store.format.f32.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.buffer.store.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.tbuffer.load.f16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.tbuffer.load.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.tbuffer.store.f16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.tbuffer.store.i8.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.raw.tbuffer.store.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.rsq.clamp.ll
…
llvm.amdgcn.s.buffer.load.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.s.setreg.ll
…
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.sbfe.ll
…
llvm.amdgcn.sdot2.ll
…
llvm.amdgcn.sdot4.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.sdot8.ll
…
llvm.amdgcn.set.inactive.ll
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect
2021-03-05 11:05:37 +01:00
llvm.amdgcn.softwqm.ll
…
llvm.amdgcn.struct.buffer.atomic.add.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
…
llvm.amdgcn.struct.buffer.atomic.fadd.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.struct.buffer.load.format.f16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.struct.buffer.load.format.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.struct.buffer.load.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.struct.buffer.store.format.f16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.struct.buffer.store.format.f32.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.struct.buffer.store.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.struct.tbuffer.load.f16.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.struct.tbuffer.load.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.trig.preop.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
llvm.amdgcn.ubfe.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
llvm.amdgcn.udot2.ll
…
llvm.amdgcn.udot4.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.udot8.ll
…
llvm.amdgcn.update.dpp.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
llvm.amdgcn.workgroup.id.ll
…
llvm.amdgcn.workitem.id.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
llvm.amdgcn.wqm.demote.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
llvm.amdgcn.wqm.ll
…
llvm.amdgcn.wqm.vote.ll
…
llvm.amdgcn.writelane.ll
…
llvm.amdgcn.wwm.ll
[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
2021-03-03 09:33:57 +01:00
llvm.powi.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
llvm.trap.ll
…
load-constant.96.ll
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
load-local.96.ll
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
load-local.128.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
load-unaligned.ll
GlobalISel: Avoid use of G_INSERT in insertParts
2021-06-08 14:44:24 -04:00
localizer.ll
AMDGPU: Use kill instruction to hint soft clause live ranges
2021-02-26 18:26:40 -05:00
lshr.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
memory-legalizer-atomic-fence.ll
…
merge-buffer-stores.ll
…
minmaxabs.ll
…
mubuf-global.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
mul.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
mul.v2i16.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
no-cse-nonlocal-convergent-instrs.mir
[MachineCSE][NFC]: Refactor and comment on preventing CSE for isConvergent instrs
2021-05-05 14:22:03 -07:00
no-legalize-atomic.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
non-entry-alloca.ll
[AMDGPU] Use s_add_i32 for address additions
2021-06-07 16:09:48 +02:00
orn2.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
postlegalizer-combiner-divrem.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postlegalizercombiner-and.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postlegalizercombiner-sbfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
postlegalizercombiner-select.mir
…
postlegalizercombiner-ubfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
prelegalizer-combiner-divrem.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizer-combiner-memcpy-inline.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
read_register.ll
…
readcyclecounter.ll
[AMDGPU] Add some GFX10.3 testing. NFC.
2021-05-11 11:21:19 +01:00
regbankcombiner-smed3.mir
AMDGPU/GlobalISel: Add integer med3 combines
2021-04-27 11:52:23 +02:00
regbankcombiner-umed3.mir
AMDGPU/GlobalISel: Add integer med3 combines
2021-04-27 11:52:23 +02:00
regbankselect-add.s16.mir
…
regbankselect-add.s32.mir
…
regbankselect-add.v2s16.mir
…
regbankselect-amdgcn-exp-compr.mir
…
regbankselect-amdgcn-exp.mir
…
regbankselect-amdgcn-s-buffer-load.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-amdgcn.ballot.i64.mir
…
regbankselect-amdgcn.class.mir
…
regbankselect-amdgcn.cvt.pkrtz.mir
…
regbankselect-amdgcn.div.fmas.mir
…
regbankselect-amdgcn.div.scale.mir
…
regbankselect-amdgcn.ds.append.mir
…
regbankselect-amdgcn.ds.bpermute.mir
…
regbankselect-amdgcn.ds.consume.mir
…
regbankselect-amdgcn.ds.gws.init.mir
…
regbankselect-amdgcn.ds.gws.sema.v.mir
…
regbankselect-amdgcn.ds.ordered.add.mir
…
regbankselect-amdgcn.ds.ordered.swap.mir
…
regbankselect-amdgcn.ds.permute.mir
…
regbankselect-amdgcn.ds.swizzle.mir
…
regbankselect-amdgcn.else.32.mir
…
regbankselect-amdgcn.else.64.mir
…
regbankselect-amdgcn.fcmp.mir
…
regbankselect-amdgcn.fmul.legacy.mir
…
regbankselect-amdgcn.groupstaticsize.mir
…
regbankselect-amdgcn.icmp.mir
…
regbankselect-amdgcn.image.load.1d.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-amdgcn.image.sample.1d.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-amdgcn.interp.mov.mir
…
regbankselect-amdgcn.interp.p1.f16.mir
…
regbankselect-amdgcn.interp.p1.mir
…
regbankselect-amdgcn.interp.p2.f16.mir
…
regbankselect-amdgcn.interp.p2.mir
…
regbankselect-amdgcn.kernarg.segment.ptr.mir
…
regbankselect-amdgcn.kill.mir
…
regbankselect-amdgcn.live.mask.mir
…
regbankselect-amdgcn.mfma.gfx90a.mir
…
regbankselect-amdgcn.mfma.mir
…
regbankselect-amdgcn.ps.live.mir
…
regbankselect-amdgcn.raw.buffer.load.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-amdgcn.readfirstlane.mir
…
regbankselect-amdgcn.readlane.mir
…
regbankselect-amdgcn.s.buffer.load.ll
GlobalISel: Preserve memory type when reducing load/store width
2021-06-30 17:05:29 -04:00
regbankselect-amdgcn.s.buffer.load.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
…
regbankselect-amdgcn.s.getpc.mir
…
regbankselect-amdgcn.s.getreg.mir
…
regbankselect-amdgcn.s.memrealtime.mir
…
regbankselect-amdgcn.s.memtime.mir
…
regbankselect-amdgcn.s.sendmsg.mir
…
regbankselect-amdgcn.s.sendmsghalt.mir
…
regbankselect-amdgcn.struct.buffer.load.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-amdgcn.struct.buffer.store.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-amdgcn.update.dpp.mir
…
regbankselect-amdgcn.wqm.demote.mir
…
regbankselect-amdgcn.wqm.mir
…
regbankselect-amdgcn.wqm.vote.mir
…
regbankselect-amdgcn.writelane.mir
…
regbankselect-amdgcn.wwm.mir
[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
2021-03-03 09:33:57 +01:00
regbankselect-amdgpu-ffbh-u32.mir
…
regbankselect-and-s1.mir
…
regbankselect-and.mir
…
regbankselect-anyext.mir
…
regbankselect-ashr.mir
…
regbankselect-atomic-cmpxchg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-add.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-and.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-fadd.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-max.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-min.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-or.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-sub.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-umax.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-umin.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-xchg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-xor.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-bitcast.mir
…
regbankselect-bitreverse.mir
[AMDGPU] Better codegen for i64 bitreverse
2021-02-26 15:51:36 +00:00
regbankselect-block-addr.mir
…
regbankselect-brcond.mir
…
regbankselect-bswap.mir
…
regbankselect-build-vector-trunc.mir
…
regbankselect-build-vector-trunc.v2s16.mir
…
regbankselect-build-vector.mir
…
regbankselect-concat-vector.mir
…
regbankselect-constant.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-copy.mir
…
regbankselect-ctlz-zero-undef.mir
…
regbankselect-ctpop.mir
…
regbankselect-cttz-zero-undef.mir
…
regbankselect-default.mir
…
regbankselect-dyn-stackalloc.mir
…
regbankselect-extract-vector-elt.mir
…
regbankselect-extract.mir
…
regbankselect-fabs.mir
…
regbankselect-fadd.mir
…
regbankselect-fcanonicalize.mir
…
regbankselect-fceil.mir
…
regbankselect-fcmp.mir
…
regbankselect-fexp2.mir
…
regbankselect-flog2.mir
…
regbankselect-fma.mir
…
regbankselect-fmul.mir
…
regbankselect-fneg.mir
…
regbankselect-fpext.mir
…
regbankselect-fptosi.mir
…
regbankselect-fptoui.mir
…
regbankselect-fptrunc.mir
…
regbankselect-frame-index.mir
…
regbankselect-freeze.mir
…
regbankselect-frint.mir
…
regbankselect-fshr.mir
…
regbankselect-fsqrt.mir
…
regbankselect-fsub.mir
…
regbankselect-icmp.mir
…
regbankselect-icmp.s16.mir
…
regbankselect-illegal-copy.mir
…
regbankselect-insert-vector-elt.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-insert.mir
…
regbankselect-intrinsic-trunc.mir
…
regbankselect-inttoptr.mir
…
regbankselect-load.mir
GlobalISel: Preserve memory type when reducing load/store width
2021-06-30 17:05:29 -04:00
regbankselect-lshr.mir
…
regbankselect-merge-values.mir
…
regbankselect-mul.mir
…
regbankselect-or.mir
…
regbankselect-phi-s1.mir
…
regbankselect-phi.mir
…
regbankselect-ptr-add.mir
…
regbankselect-ptrmask.mir
…
regbankselect-ptrtoint.mir
…
regbankselect-reg-sequence.mir
…
regbankselect-sadde.mir
…
regbankselect-sbfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
regbankselect-select.mir
…
regbankselect-sext-inreg.mir
…
regbankselect-sext.mir
…
regbankselect-sextload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-shl.mir
…
regbankselect-shuffle-vector.mir
…
regbankselect-sitofp.mir
…
regbankselect-smax.mir
…
regbankselect-smin.mir
…
regbankselect-smulh.mir
…
regbankselect-split-scalar-load-metadata.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-ssube.mir
…
regbankselect-sub.mir
…
regbankselect-trunc.mir
…
regbankselect-uadde.mir
…
regbankselect-uaddo.mir
…
regbankselect-ubfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
regbankselect-uitofp.mir
…
regbankselect-umax.mir
…
regbankselect-umin.mir
…
regbankselect-umulh.mir
…
regbankselect-uniform-load-noclobber.mir
GlobalISel: Preserve memory type when reducing load/store width
2021-06-30 17:05:29 -04:00
regbankselect-unmerge-values.mir
…
regbankselect-usube.mir
…
regbankselect-usubo.mir
…
regbankselect-waterfall-agpr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-widen-scalar-loads.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-xor.mir
…
regbankselect-zext.mir
…
regbankselect-zextload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ret.ll
…
roundeven.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
saddsat.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
sbfx.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
sdiv.i32.ll
…
sdiv.i64.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
sdivrem.ll
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
shader-epilogs.ll
…
shl-ext-reduce.ll
[GISel] Eliminate redundant bitmasking
2021-06-17 12:53:00 -07:00
shl.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
shlN_add.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00
smed3.ll
AMDGPU/GlobalISel: Add integer med3 combines
2021-04-27 11:52:23 +02:00
smrd.ll
…
srem.i32.ll
…
srem.i64.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
ssubsat.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
store-local.96.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
store-local.128.ll
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
2021-04-26 17:21:49 -04:00
trunc.ll
…
uaddsat.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
ubfx.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
udiv.i32.ll
…
udiv.i64.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
udivrem.ll
GlobalISel: Use LLT in memory legality queries
2021-06-30 17:44:13 -04:00
umed3.ll
AMDGPU/GlobalISel: Add integer med3 combines
2021-04-27 11:52:23 +02:00
urem.i32.ll
AMDGPU/GlobalISel: Enable CSE in pre-legalizer combiner
2021-03-21 10:07:37 -04:00
urem.i64.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
usubsat.ll
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
widen-i8-i16-scalar-loads.ll
[AMDGPU][GlobalISel] Widen 1 and 2 byte scalar loads
2021-05-05 15:18:19 -07:00
write_register.ll
…
xnor.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
zextload.ll
[AMDGPU] Extend gfx10 test coverage. NFC.
2021-03-29 11:13:55 +02:00