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All instructions that can raise fp exceptions also read FPCR, with the only other instructions that interact with it being the MSR/MRS to write/read FPCR. Introducing an FPCR register also requires adjusting invalidateWindowsRegisterPairing in AArch64FrameLowering.cpp to use the encoded value of registers instead of their enum value, as the enum value is based on the alphabetical order of register names and now FPCR is placed between FP and LR. This change unfortunately means a large number of mir tests need to be adjusted due to instructions now requiring an implicit fpcr operand to be present. Differential Revision: https://reviews.llvm.org/D121929
This directory contains tests for the MIR file format parser and printer. It was necessary to split the tests across different targets as no single target covers all features available in machine IR. Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As a rule of thumb this directory should only contain tests using 'llc -run-pass none'.