Matt Arsenault 4aa4005e04 AMDGPU: Make copysign with matching v2f16/v2bf16 inputs legal (#142173) ...

Fixes #141931

2025-05-31 08:06:49 +02:00

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AArch64

[AArch64] Enable fixed-length vector support for partial-reductions (#142032)

2025-05-30 17:47:31 +01:00

AMDGPU

AMDGPU: Make copysign with matching v2f16/v2bf16 inputs legal (#142173)

2025-05-31 08:06:49 +02:00

ARC

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ARM

[ARM]: codegen llvm.roundeven.v* (#141786)

2025-05-30 19:36:29 +01:00

AVR

[LangRef] Comment on validity of volatile ops on null (#139803)

2025-05-22 15:12:34 +02:00

BPF

[BPF] Allow struct pointee member btf generation with annotations (#141719)

2025-05-28 14:36:10 -07:00

CSKY

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DirectX

[HLSL] Diagnose overlapping resource bindings (#140982)

2025-05-30 13:22:25 -07:00

Generic

CodeGen: Convert some assorted errors to use reportFatalUsageError (#142031)

2025-05-30 08:06:53 +02:00

Hexagon

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Inputs

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Lanai

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LoongArch

[LoongArch] Fix out-of-range assert in DAG constant getting (#141586)

2025-05-28 11:06:08 +08:00

M68k

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Mips

[MIPS] Reland Add FeatureMSA to i6400 and i6500 cores (#134985) (#141730)

2025-05-30 22:33:34 -04:00

MIR

[NVPTX] Cleanup ISel code after float register removal, use BasicNVPTXInst (#141711)

2025-05-29 12:24:31 -07:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Cleanup ISel code after float register removal, use BasicNVPTXInst (#141711)

2025-05-29 12:24:31 -07:00

PowerPC

Revert "[PowerPC] extend smaller splats into bigger splats (#141282)"

2025-05-29 01:10:55 -04:00

RISCV

[DAGCombiner] Teach SearchForAndLoads to handle an AND with 2 constant operands. (#142062)

2025-05-30 16:00:43 -07:00

SPARC

[SPARC] Use op-then-halve instructions when we have VIS3

2025-05-23 22:44:05 +07:00

SPIRV

[SPIR-V] Consistent handling of TargetExtTypes in emit-intrinsics (#135682)

2025-05-29 18:00:16 -04:00

SystemZ

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Thumb

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Thumb2

[ARM]: codegen llvm.roundeven.v* (#141786)

2025-05-30 19:36:29 +01:00

VE

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WebAssembly

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WinCFGuard

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WinEH

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X86

[SDAG] Remove noundef workaround for range metadata/attributes (#141745)

2025-05-30 10:56:49 +02:00

XCore

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Xtensa

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