ee4ba9f3a1
Unfortunately, it seems we really do need to take the long route; start from the "merge" block, find (all the) "dispatch" blocks, and deal with each "dispatch" block separately, instead of simply starting from each "dispatch" block like it would logically make sense, otherwise we run into a number of other missing folds around `switch` formation, missing sinking/hoisting and phase ordering. This reverts commit85628ce75b. This reverts commitc5fff90953. This reverts commit34a98e1046. This reverts commit1e353f0922.
30 lines
814 B
LLVM
30 lines
814 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumb-- %s -o - | FileCheck %s
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; This test checks that if-conversion pass is unconditionally added to the pass
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; pipeline and is conditionally executed based on the per-function targert-cpu
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; attribute.
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define i32 @test_ifcvt(i32 %a, i32 %b) #0 {
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; CHECK-LABEL: test_ifcvt:
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; CHECK: @ %bb.0: @ %common.ret
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; CHECK-NEXT: movs r2, #1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: moveq.w r2, #-1
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; CHECK-NEXT: adds r0, r1, r2
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; CHECK-NEXT: bx lr
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%tmp2 = icmp eq i32 %a, 0
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br i1 %tmp2, label %cond_false, label %cond_true
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cond_true:
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%tmp5 = add i32 %b, 1
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ret i32 %tmp5
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cond_false:
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%tmp7 = add i32 %b, -1
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ret i32 %tmp7
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}
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attributes #0 = { "target-cpu"="cortex-a8" }
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