6f7e940c2d
DecoderEmitter and CodeEmitterGen perform repeated linear walks over the entire instruction list. This patch eliminates two more such walks. The eliminated traversals visit every instruction merely to determine whether the target has variable length encodings. For a target with variable length encodings, the original any_of will terminate quickly. But all targets other than M68k use fixed length encodings and thus any_of must visit the entire instruction list.
256 lines
8.2 KiB
C++
256 lines
8.2 KiB
C++
//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines wrappers for the Target class and related global
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// functionality. This makes it easier to access the data and provides a single
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// place that needs to check it for validity. All of these classes abort
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// on error conditions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
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#define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
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#include "CodeGenHwModes.h"
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#include "CodeGenInstruction.h"
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#include "InfoByHwMode.h"
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#include "SDNodeProperties.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGenTypes/MachineValueType.h"
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#include <cassert>
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#include <memory>
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#include <optional>
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#include <string>
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#include <vector>
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namespace llvm {
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class RecordKeeper;
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class Record;
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class CodeGenRegBank;
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class CodeGenRegister;
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class CodeGenRegisterClass;
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class CodeGenSchedModels;
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class CodeGenSubRegIndex;
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/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
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/// record corresponds to.
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MVT::SimpleValueType getValueType(const Record *Rec);
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StringRef getName(MVT::SimpleValueType T);
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StringRef getEnumName(MVT::SimpleValueType T);
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/// getQualifiedName - Return the name of the specified record, with a
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/// namespace qualifier if the record contains one.
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std::string getQualifiedName(const Record *R);
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/// CodeGenTarget - This class corresponds to the Target class in the .td files.
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///
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class CodeGenTarget {
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RecordKeeper &Records;
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Record *TargetRec;
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mutable DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>>
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Instructions;
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mutable std::unique_ptr<CodeGenRegBank> RegBank;
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mutable std::vector<Record *> RegAltNameIndices;
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mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
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CodeGenHwModes CGH;
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std::vector<Record *> MacroFusions;
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mutable bool HasVariableLengthEncodings = false;
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void ReadRegAltNameIndices() const;
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void ReadInstructions() const;
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void ReadLegalValueTypes() const;
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mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
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mutable StringRef InstNamespace;
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mutable std::vector<const CodeGenInstruction *> InstrsByEnum;
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mutable unsigned NumPseudoInstructions = 0;
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public:
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CodeGenTarget(RecordKeeper &Records);
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~CodeGenTarget();
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Record *getTargetRecord() const { return TargetRec; }
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StringRef getName() const;
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/// getInstNamespace - Return the target-specific instruction namespace.
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///
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StringRef getInstNamespace() const;
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/// getRegNamespace - Return the target-specific register namespace.
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StringRef getRegNamespace() const;
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/// getInstructionSet - Return the InstructionSet object.
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///
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Record *getInstructionSet() const;
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/// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for
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/// this target.
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///
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bool getAllowRegisterRenaming() const;
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/// getAsmParser - Return the AssemblyParser definition for this target.
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///
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Record *getAsmParser() const;
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/// getAsmParserVariant - Return the AssemblyParserVariant definition for
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/// this target.
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///
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Record *getAsmParserVariant(unsigned i) const;
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/// getAsmParserVariantCount - Return the AssemblyParserVariant definition
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/// available for this target.
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///
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unsigned getAsmParserVariantCount() const;
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *getAsmWriter() const;
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/// getRegBank - Return the register bank description.
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CodeGenRegBank &getRegBank() const;
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/// Return the largest register class on \p RegBank which supports \p Ty and
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/// covers \p SubIdx if it exists.
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std::optional<CodeGenRegisterClass *>
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getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
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const CodeGenSubRegIndex *SubIdx,
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bool MustBeAllocatable = false) const;
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/// getRegisterByName - If there is a register with the specific AsmName,
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/// return it.
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const CodeGenRegister *getRegisterByName(StringRef Name) const;
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const std::vector<Record *> &getRegAltNameIndices() const {
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if (RegAltNameIndices.empty())
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ReadRegAltNameIndices();
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return RegAltNameIndices;
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}
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const CodeGenRegisterClass &getRegisterClass(Record *R) const;
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/// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
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/// specified physical register.
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std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
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ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
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if (LegalValueTypes.empty())
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ReadLegalValueTypes();
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return LegalValueTypes;
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}
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CodeGenSchedModels &getSchedModels() const;
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const CodeGenHwModes &getHwModes() const { return CGH; }
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bool hasMacroFusion() const { return !MacroFusions.empty(); }
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const std::vector<Record *> getMacroFusions() const { return MacroFusions; }
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private:
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DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> &
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getInstructions() const {
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if (Instructions.empty())
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ReadInstructions();
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return Instructions;
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}
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public:
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CodeGenInstruction &getInstruction(const Record *InstRec) const {
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if (Instructions.empty())
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ReadInstructions();
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auto I = Instructions.find(InstRec);
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assert(I != Instructions.end() && "Not an instruction");
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return *I->second;
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}
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/// Returns the number of predefined instructions.
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static unsigned getNumFixedInstructions();
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/// Returns the number of pseudo instructions.
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unsigned getNumPseudoInstructions() const {
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if (InstrsByEnum.empty())
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ComputeInstrsByEnum();
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return NumPseudoInstructions;
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}
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/// Return all of the instructions defined by the target, ordered by their
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/// enum value.
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/// The following order of instructions is also guaranteed:
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/// - fixed / generic instructions as declared in TargetOpcodes.def, in order;
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/// - pseudo instructions in lexicographical order sorted by name;
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/// - other instructions in lexicographical order sorted by name.
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ArrayRef<const CodeGenInstruction *> getInstructionsByEnumValue() const {
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if (InstrsByEnum.empty())
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ComputeInstrsByEnum();
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return InstrsByEnum;
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}
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/// Return the integer enum value corresponding to this instruction record.
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unsigned getInstrIntValue(const Record *R) const {
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if (InstrsByEnum.empty())
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ComputeInstrsByEnum();
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return getInstruction(R).EnumVal;
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}
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typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator;
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inst_iterator inst_begin() const {
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return getInstructionsByEnumValue().begin();
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}
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inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
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/// Return whether instructions have variable length encodings on this target.
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bool hasVariableLengthEncodings() const { return HasVariableLengthEncodings; }
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/// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
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///
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bool isLittleEndianEncoding() const;
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/// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
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/// encodings, reverse the bit order of all instructions.
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void reverseBitsForLittleEndianEncoding();
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/// guessInstructionProperties - should we just guess unset instruction
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/// properties?
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bool guessInstructionProperties() const;
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private:
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void ComputeInstrsByEnum() const;
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};
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/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
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/// tablegen class in TargetSelectionDAG.td
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class ComplexPattern {
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Record *Ty;
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unsigned NumOperands;
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std::string SelectFunc;
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std::vector<Record *> RootNodes;
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unsigned Properties; // Node properties
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unsigned Complexity;
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public:
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ComplexPattern(Record *R);
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Record *getValueType() const { return Ty; }
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unsigned getNumOperands() const { return NumOperands; }
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const std::string &getSelectFunc() const { return SelectFunc; }
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const std::vector<Record *> &getRootNodes() const { return RootNodes; }
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bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
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unsigned getComplexity() const { return Complexity; }
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};
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} // namespace llvm
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#endif
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