54f631d116
Implement an abstraction to specify precise overload types supported by DXIL ops. These overload types are typically a subset of LLVM intrinsics. Implement the corresponding changes in DXILEmitter backend. Add tests to verify expected errors for unsupported overload types at code generation time. Add tests to check for correct overload error output.
488 lines
17 KiB
C++
488 lines
17 KiB
C++
//===- DXILEmitter.cpp - DXIL operation Emitter ---------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// DXILEmitter uses the descriptions of DXIL operation to construct enum and
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// helper functions for DXIL operation.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "SequenceToOffsetTable.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/CodeGenTypes/MachineValueType.h"
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#include "llvm/Support/DXILABI.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <string>
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using namespace llvm;
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using namespace llvm::dxil;
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namespace {
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struct DXILShaderModel {
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int Major = 0;
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int Minor = 0;
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};
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struct DXILOperationDesc {
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std::string OpName; // name of DXIL operation
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int OpCode; // ID of DXIL operation
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StringRef OpClass; // name of the opcode class
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StringRef Doc; // the documentation description of this instruction
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SmallVector<Record *> OpTypes; // Vector of operand type records -
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// return type is at index 0
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SmallVector<std::string>
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OpAttributes; // operation attribute represented as strings
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StringRef Intrinsic; // The llvm intrinsic map to OpName. Default is "" which
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// means no map exists
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bool IsDeriv = false; // whether this is some kind of derivative
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bool IsGradient = false; // whether this requires a gradient calculation
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bool IsFeedback = false; // whether this is a sampler feedback op
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bool IsWave =
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false; // whether this requires in-wave, cross-lane functionality
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bool RequiresUniformInputs = false; // whether this operation requires that
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// all of its inputs are uniform across
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// the wave
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SmallVector<StringRef, 4>
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ShaderStages; // shader stages to which this applies, empty for all.
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DXILShaderModel ShaderModel; // minimum shader model required
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DXILShaderModel ShaderModelTranslated; // minimum shader model required with
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// translation by linker
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int OverloadParamIndex; // Index of parameter with overload type.
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// -1 : no overload types
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SmallVector<StringRef, 4> counters; // counters for this inst.
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DXILOperationDesc(const Record *);
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};
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} // end anonymous namespace
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/// Return dxil::ParameterKind corresponding to input LLVMType record
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///
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/// \param R TableGen def record of class LLVMType
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/// \return ParameterKind As defined in llvm/Support/DXILABI.h
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static ParameterKind getParameterKind(const Record *R) {
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auto VTRec = R->getValueAsDef("VT");
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switch (getValueType(VTRec)) {
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case MVT::isVoid:
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return ParameterKind::VOID;
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case MVT::f16:
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return ParameterKind::HALF;
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case MVT::f32:
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return ParameterKind::FLOAT;
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case MVT::f64:
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return ParameterKind::DOUBLE;
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case MVT::i1:
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return ParameterKind::I1;
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case MVT::i8:
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return ParameterKind::I8;
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case MVT::i16:
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return ParameterKind::I16;
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case MVT::i32:
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return ParameterKind::I32;
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case MVT::fAny:
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case MVT::iAny:
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return ParameterKind::OVERLOAD;
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case MVT::Other:
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// Handle DXIL-specific overload types
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if (R->getValueAsInt("isHalfOrFloat") || R->getValueAsInt("isI16OrI32")) {
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return ParameterKind::OVERLOAD;
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}
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LLVM_FALLTHROUGH;
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default:
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llvm_unreachable("Support for specified DXIL Type not yet implemented");
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}
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}
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/// Construct an object using the DXIL Operation records specified
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/// in DXIL.td. This serves as the single source of reference of
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/// the information extracted from the specified Record R, for
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/// C++ code generated by this TableGen backend.
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// \param R Object representing TableGen record of a DXIL Operation
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DXILOperationDesc::DXILOperationDesc(const Record *R) {
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OpName = R->getNameInitAsString();
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OpCode = R->getValueAsInt("OpCode");
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Doc = R->getValueAsString("Doc");
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auto TypeRecs = R->getValueAsListOfDefs("OpTypes");
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unsigned TypeRecsSize = TypeRecs.size();
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// Populate OpTypes with return type and parameter types
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// Parameter indices of overloaded parameters.
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// This vector contains overload parameters in the order order used to
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// resolve an LLVMMatchType in accordance with convention outlined in
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// the comment before the definition of class LLVMMatchType in
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// llvm/IR/Intrinsics.td
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SmallVector<int> OverloadParamIndices;
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for (unsigned i = 0; i < TypeRecsSize; i++) {
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auto TR = TypeRecs[i];
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// Track operation parameter indices of any overload types
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auto isAny = TR->getValueAsInt("isAny");
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if (isAny == 1) {
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// TODO: At present it is expected that all overload types in a DXIL Op
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// are of the same type. Hence, OverloadParamIndices will have only one
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// element. This implies we do not need a vector. However, until more
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// (all?) DXIL Ops are added in DXIL.td, a vector is being used to flag
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// cases this assumption would not hold.
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if (!OverloadParamIndices.empty()) {
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bool knownType = true;
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// Ensure that the same overload type registered earlier is being used
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for (auto Idx : OverloadParamIndices) {
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if (TR != TypeRecs[Idx]) {
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knownType = false;
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break;
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}
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}
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if (!knownType) {
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report_fatal_error("Specification of multiple differing overload "
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"parameter types not yet supported",
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false);
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}
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} else {
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OverloadParamIndices.push_back(i);
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}
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}
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// Populate OpTypes array according to the type specification
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if (TR->isAnonymous()) {
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// Check prior overload types exist
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assert(!OverloadParamIndices.empty() &&
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"No prior overloaded parameter found to match.");
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// Get the parameter index of anonymous type, TR, references
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auto OLParamIndex = TR->getValueAsInt("Number");
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// Resolve and insert the type to that at OLParamIndex
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OpTypes.emplace_back(TypeRecs[OLParamIndex]);
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} else {
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// A non-anonymous type. Just record it in OpTypes
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OpTypes.emplace_back(TR);
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}
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}
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// Set the index of the overload parameter, if any.
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OverloadParamIndex = -1; // default; indicating none
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if (!OverloadParamIndices.empty()) {
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if (OverloadParamIndices.size() > 1)
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report_fatal_error("Multiple overload type specification not supported",
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false);
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OverloadParamIndex = OverloadParamIndices[0];
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}
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// Get the operation class
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OpClass = R->getValueAsDef("OpClass")->getName();
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if (R->getValue("LLVMIntrinsic")) {
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auto *IntrinsicDef = R->getValueAsDef("LLVMIntrinsic");
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auto DefName = IntrinsicDef->getName();
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assert(DefName.starts_with("int_") && "invalid intrinsic name");
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// Remove the int_ from intrinsic name.
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Intrinsic = DefName.substr(4);
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// TODO: For now, assume that attributes of DXIL Operation are the same as
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// that of the intrinsic. Deviations are expected to be encoded in TableGen
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// record specification and handled accordingly here. Support to be added
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// as needed.
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auto IntrPropList = IntrinsicDef->getValueAsListInit("IntrProperties");
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auto IntrPropListSize = IntrPropList->size();
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for (unsigned i = 0; i < IntrPropListSize; i++) {
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OpAttributes.emplace_back(IntrPropList->getElement(i)->getAsString());
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}
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}
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}
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/// Return a string representation of ParameterKind enum
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/// \param Kind Parameter Kind enum value
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/// \return std::string string representation of input Kind
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static std::string getParameterKindStr(ParameterKind Kind) {
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switch (Kind) {
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case ParameterKind::INVALID:
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return "INVALID";
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case ParameterKind::VOID:
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return "VOID";
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case ParameterKind::HALF:
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return "HALF";
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case ParameterKind::FLOAT:
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return "FLOAT";
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case ParameterKind::DOUBLE:
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return "DOUBLE";
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case ParameterKind::I1:
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return "I1";
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case ParameterKind::I8:
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return "I8";
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case ParameterKind::I16:
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return "I16";
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case ParameterKind::I32:
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return "I32";
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case ParameterKind::I64:
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return "I64";
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case ParameterKind::OVERLOAD:
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return "OVERLOAD";
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case ParameterKind::CBUFFER_RET:
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return "CBUFFER_RET";
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case ParameterKind::RESOURCE_RET:
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return "RESOURCE_RET";
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case ParameterKind::DXIL_HANDLE:
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return "DXIL_HANDLE";
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}
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llvm_unreachable("Unknown llvm::dxil::ParameterKind enum");
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}
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/// Return a string representation of OverloadKind enum that maps to
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/// input LLVMType record
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/// \param R TableGen def record of class LLVMType
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/// \return std::string string representation of OverloadKind
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static std::string getOverloadKindStr(const Record *R) {
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auto VTRec = R->getValueAsDef("VT");
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switch (getValueType(VTRec)) {
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case MVT::isVoid:
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return "OverloadKind::VOID";
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case MVT::f16:
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return "OverloadKind::HALF";
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case MVT::f32:
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return "OverloadKind::FLOAT";
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case MVT::f64:
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return "OverloadKind::DOUBLE";
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case MVT::i1:
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return "OverloadKind::I1";
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case MVT::i8:
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return "OverloadKind::I8";
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case MVT::i16:
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return "OverloadKind::I16";
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case MVT::i32:
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return "OverloadKind::I32";
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case MVT::i64:
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return "OverloadKind::I64";
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case MVT::iAny:
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return "OverloadKind::I16 | OverloadKind::I32 | OverloadKind::I64";
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case MVT::fAny:
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return "OverloadKind::HALF | OverloadKind::FLOAT | OverloadKind::DOUBLE";
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case MVT::Other:
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// Handle DXIL-specific overload types
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{
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if (R->getValueAsInt("isHalfOrFloat")) {
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return "OverloadKind::HALF | OverloadKind::FLOAT";
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} else if (R->getValueAsInt("isI16OrI32")) {
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return "OverloadKind::I16 | OverloadKind::I32";
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}
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}
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LLVM_FALLTHROUGH;
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default:
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llvm_unreachable(
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"Support for specified parameter OverloadKind not yet implemented");
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}
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}
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/// Emit Enums of DXIL Ops
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/// \param A vector of DXIL Ops
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/// \param Output stream
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static void emitDXILEnums(std::vector<DXILOperationDesc> &Ops,
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raw_ostream &OS) {
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// Sort by OpCode
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llvm::sort(Ops, [](DXILOperationDesc &A, DXILOperationDesc &B) {
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return A.OpCode < B.OpCode;
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});
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OS << "// Enumeration for operations specified by DXIL\n";
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OS << "enum class OpCode : unsigned {\n";
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for (auto &Op : Ops) {
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// Name = ID, // Doc
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OS << Op.OpName << " = " << Op.OpCode << ", // " << Op.Doc << "\n";
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}
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OS << "\n};\n\n";
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OS << "// Groups for DXIL operations with equivalent function templates\n";
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OS << "enum class OpCodeClass : unsigned {\n";
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// Build an OpClass set to print
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SmallSet<StringRef, 2> OpClassSet;
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for (auto &Op : Ops) {
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OpClassSet.insert(Op.OpClass);
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}
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for (auto &C : OpClassSet) {
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OS << C << ",\n";
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}
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OS << "\n};\n\n";
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}
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/// Emit map of DXIL operation to LLVM or DirectX intrinsic
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/// \param A vector of DXIL Ops
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/// \param Output stream
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static void emitDXILIntrinsicMap(std::vector<DXILOperationDesc> &Ops,
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raw_ostream &OS) {
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OS << "\n";
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// FIXME: use array instead of SmallDenseMap.
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OS << "static const SmallDenseMap<Intrinsic::ID, dxil::OpCode> LowerMap = "
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"{\n";
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for (auto &Op : Ops) {
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if (Op.Intrinsic.empty())
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continue;
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// {Intrinsic::sin, dxil::OpCode::Sin},
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OS << " { Intrinsic::" << Op.Intrinsic << ", dxil::OpCode::" << Op.OpName
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<< "},\n";
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}
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OS << "};\n";
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OS << "\n";
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}
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/// Convert operation attribute string to Attribute enum
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///
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/// \param Attr string reference
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/// \return std::string Attribute enum string
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static std::string emitDXILOperationAttr(SmallVector<std::string> Attrs) {
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for (auto Attr : Attrs) {
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// TODO: For now just recognize IntrNoMem and IntrReadMem as valid and
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// ignore others.
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if (Attr == "IntrNoMem") {
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return "Attribute::ReadNone";
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} else if (Attr == "IntrReadMem") {
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return "Attribute::ReadOnly";
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}
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}
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return "Attribute::None";
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}
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/// Emit DXIL operation table
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/// \param A vector of DXIL Ops
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/// \param Output stream
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static void emitDXILOperationTable(std::vector<DXILOperationDesc> &Ops,
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raw_ostream &OS) {
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// Sort by OpCode.
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llvm::sort(Ops, [](DXILOperationDesc &A, DXILOperationDesc &B) {
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return A.OpCode < B.OpCode;
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});
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// Collect Names.
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SequenceToOffsetTable<std::string> OpClassStrings;
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SequenceToOffsetTable<std::string> OpStrings;
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SequenceToOffsetTable<SmallVector<ParameterKind>> Parameters;
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StringMap<SmallVector<ParameterKind>> ParameterMap;
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StringSet<> ClassSet;
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for (auto &Op : Ops) {
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OpStrings.add(Op.OpName);
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if (ClassSet.contains(Op.OpClass))
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continue;
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ClassSet.insert(Op.OpClass);
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OpClassStrings.add(Op.OpClass.data());
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SmallVector<ParameterKind> ParamKindVec;
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// ParamKindVec is a vector of parameters. Skip return type at index 0
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for (unsigned i = 1; i < Op.OpTypes.size(); i++) {
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ParamKindVec.emplace_back(getParameterKind(Op.OpTypes[i]));
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}
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ParameterMap[Op.OpClass] = ParamKindVec;
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Parameters.add(ParamKindVec);
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}
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// Layout names.
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OpStrings.layout();
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OpClassStrings.layout();
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Parameters.layout();
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// Emit the DXIL operation table.
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//{dxil::OpCode::Sin, OpCodeNameIndex, OpCodeClass::unary,
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// OpCodeClassNameIndex,
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// OverloadKind::FLOAT | OverloadKind::HALF, Attribute::AttrKind::ReadNone, 0,
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// 3, ParameterTableOffset},
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OS << "static const OpCodeProperty *getOpCodeProperty(dxil::OpCode Op) "
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"{\n";
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OS << " static const OpCodeProperty OpCodeProps[] = {\n";
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for (auto &Op : Ops) {
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OS << " { dxil::OpCode::" << Op.OpName << ", " << OpStrings.get(Op.OpName)
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<< ", OpCodeClass::" << Op.OpClass << ", "
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<< OpClassStrings.get(Op.OpClass.data()) << ", "
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<< getOverloadKindStr(Op.OpTypes[0]) << ", "
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<< emitDXILOperationAttr(Op.OpAttributes) << ", "
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<< Op.OverloadParamIndex << ", " << Op.OpTypes.size() - 1 << ", "
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<< Parameters.get(ParameterMap[Op.OpClass]) << " },\n";
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}
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OS << " };\n";
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OS << " // FIXME: change search to indexing with\n";
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OS << " // Op once all DXIL operations are added.\n";
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OS << " OpCodeProperty TmpProp;\n";
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OS << " TmpProp.OpCode = Op;\n";
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OS << " const OpCodeProperty *Prop =\n";
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OS << " llvm::lower_bound(OpCodeProps, TmpProp,\n";
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OS << " [](const OpCodeProperty &A, const "
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"OpCodeProperty &B) {\n";
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OS << " return A.OpCode < B.OpCode;\n";
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OS << " });\n";
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OS << " assert(Prop && \"failed to find OpCodeProperty\");\n";
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OS << " return Prop;\n";
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OS << "}\n\n";
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// Emit the string tables.
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OS << "static const char *getOpCodeName(dxil::OpCode Op) {\n\n";
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OpStrings.emitStringLiteralDef(OS,
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" static const char DXILOpCodeNameTable[]");
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OS << " auto *Prop = getOpCodeProperty(Op);\n";
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OS << " unsigned Index = Prop->OpCodeNameOffset;\n";
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OS << " return DXILOpCodeNameTable + Index;\n";
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OS << "}\n\n";
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OS << "static const char *getOpCodeClassName(const OpCodeProperty &Prop) "
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"{\n\n";
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OpClassStrings.emitStringLiteralDef(
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OS, " static const char DXILOpCodeClassNameTable[]");
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OS << " unsigned Index = Prop.OpCodeClassNameOffset;\n";
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OS << " return DXILOpCodeClassNameTable + Index;\n";
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OS << "}\n ";
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OS << "static const ParameterKind *getOpCodeParameterKind(const "
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"OpCodeProperty &Prop) "
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"{\n\n";
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OS << " static const ParameterKind DXILOpParameterKindTable[] = {\n";
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Parameters.emit(
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OS,
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[](raw_ostream &ParamOS, ParameterKind Kind) {
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ParamOS << "ParameterKind::" << getParameterKindStr(Kind);
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},
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"ParameterKind::INVALID");
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OS << " };\n\n";
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OS << " unsigned Index = Prop.ParameterTableOffset;\n";
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OS << " return DXILOpParameterKindTable + Index;\n";
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OS << "}\n ";
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}
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/// Entry function call that invokes the functionality of this TableGen backend
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/// \param Records TableGen records of DXIL Operations defined in DXIL.td
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/// \param OS output stream
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static void EmitDXILOperation(RecordKeeper &Records, raw_ostream &OS) {
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OS << "// Generated code, do not edit.\n";
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OS << "\n";
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// Get all DXIL Ops to intrinsic mapping records
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std::vector<Record *> OpIntrMaps =
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Records.getAllDerivedDefinitions("DXILOpMapping");
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std::vector<DXILOperationDesc> DXILOps;
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for (auto *Record : OpIntrMaps) {
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DXILOps.emplace_back(DXILOperationDesc(Record));
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}
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OS << "#ifdef DXIL_OP_ENUM\n";
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emitDXILEnums(DXILOps, OS);
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OS << "#endif\n\n";
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OS << "#ifdef DXIL_OP_INTRINSIC_MAP\n";
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emitDXILIntrinsicMap(DXILOps, OS);
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OS << "#endif\n\n";
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OS << "#ifdef DXIL_OP_OPERATION_TABLE\n";
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emitDXILOperationTable(DXILOps, OS);
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OS << "#endif\n\n";
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}
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static TableGen::Emitter::Opt X("gen-dxil-operation", EmitDXILOperation,
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"Generate DXIL operation information");
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