4ba4816b97
This also takes the push/pop syntax another step forward, introducing stack slot numbers to make it easier to see how expressions are connected. For example, the value pushed in $push7 is popped in $pop7. And, this begins an experiment with making get_local and set_local implicit when an operation directly uses or defines a register. This greatly reduces clutter. If this experiment succeeds, it may make sense to do this for const instructions as well. And, this introduces more special code for ARGUMENTS; hopefully this code will soon be obviated by proper support for live-in virtual registers. llvm-svn: 253465
141 lines
4.1 KiB
C++
141 lines
4.1 KiB
C++
//===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file contains the WebAssembly implementation of the
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/// TargetInstrInfo class.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyInstrInfo.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-instr-info"
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#define GET_INSTRINFO_CTOR_DTOR
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#include "WebAssemblyGenInstrInfo.inc"
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WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
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: RI(STI.getTargetTriple()) {}
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void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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DebugLoc DL, unsigned DestReg,
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unsigned SrcReg, bool KillSrc) const {
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const TargetRegisterClass *RC =
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MBB.getParent()->getRegInfo().getRegClass(SrcReg);
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unsigned SetLocalOpcode;
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if (RC == &WebAssembly::I32RegClass)
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SetLocalOpcode = WebAssembly::SET_LOCAL_I32;
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else if (RC == &WebAssembly::I64RegClass)
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SetLocalOpcode = WebAssembly::SET_LOCAL_I64;
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else if (RC == &WebAssembly::F32RegClass)
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SetLocalOpcode = WebAssembly::SET_LOCAL_F32;
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else if (RC == &WebAssembly::F64RegClass)
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SetLocalOpcode = WebAssembly::SET_LOCAL_F64;
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else
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llvm_unreachable("Unexpected register class");
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BuildMI(MBB, I, DL, get(SetLocalOpcode), DestReg)
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.addReg(SrcReg, KillSrc ? RegState::Kill : 0);
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}
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// Branch analysis.
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bool WebAssemblyInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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bool HaveCond = false;
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for (MachineInstr &MI : iterator_range<MachineBasicBlock::instr_iterator>(
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MBB.getFirstInstrTerminator(), MBB.instr_end())) {
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switch (MI.getOpcode()) {
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default:
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// Unhandled instruction; bail out.
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return true;
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case WebAssembly::BR_IF:
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if (HaveCond)
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return true;
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Cond.push_back(MI.getOperand(0));
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TBB = MI.getOperand(1).getMBB();
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HaveCond = true;
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break;
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case WebAssembly::BR:
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if (!HaveCond)
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TBB = MI.getOperand(0).getMBB();
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else
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FBB = MI.getOperand(0).getMBB();
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break;
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}
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if (MI.isBarrier())
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break;
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}
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return false;
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}
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unsigned WebAssemblyInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::instr_iterator I = MBB.instr_end();
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unsigned Count = 0;
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while (I != MBB.instr_begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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if (!I->isTerminator())
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break;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.instr_end();
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++Count;
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}
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return Count;
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}
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unsigned WebAssemblyInstrInfo::InsertBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
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assert(Cond.size() <= 1);
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if (Cond.empty()) {
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if (!TBB)
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return 0;
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BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
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return 1;
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}
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BuildMI(&MBB, DL, get(WebAssembly::BR_IF))
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.addOperand(Cond[0])
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.addMBB(TBB);
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if (!FBB)
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return 1;
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BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
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return 2;
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}
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bool WebAssemblyInstrInfo::ReverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 1);
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// TODO: Add branch reversal here... And re-enable MachineBlockPlacementID
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// when we do.
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return true;
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}
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