db5a11f698
The two-address instruction pass will convert these back to v_mad_f32 if necessary. Differential Revision: http://reviews.llvm.org/D11060 llvm-svn: 242038
14 lines
623 B
LLVM
14 lines
623 B
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare float @llvm.AMDGPU.lrp(float, float, float) nounwind readnone
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; FUNC-LABEL: {{^}}test_lrp:
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; SI: v_sub_f32
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; SI: v_mac_f32_e32
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define void @test_lrp(float addrspace(1)* %out, float %src0, float %src1, float %src2) nounwind {
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%mad = call float @llvm.AMDGPU.lrp(float %src0, float %src1, float %src2) nounwind readnone
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store float %mad, float addrspace(1)* %out, align 4
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ret void
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}
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