5cee34013c
Future CPU will include support for prefixed instructions. These prefixed instructions are formed by a 4 byte prefix immediately followed by a 4 byte instruction effectively making an 8 byte instruction. The new instruction paddi is a prefixed form of addi. This patch adds paddi and all of the support required for that instruction. The majority of the patch deals with supporting the new prefixed instructions. The addition of paddi is mainly to allow for testing. Differential Revision: https://reviews.llvm.org/D72569
20 lines
603 B
LLVM
20 lines
603 B
LLVM
; RUN: llc -mattr=prefix-instrs -verify-machineinstrs \
|
|
; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
|
|
; RUN: %s -o - 2>&1 | FileCheck %s
|
|
; RUN: llc -mattr=prefix-instrs -verify-machineinstrs \
|
|
; RUN: -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \
|
|
; RUN: %s -o - 2>&1 | FileCheck %s
|
|
|
|
define dso_local signext i32 @f() {
|
|
entry:
|
|
ret i32 0
|
|
}
|
|
|
|
; Make sure that all of the features listed are recognized.
|
|
; CHECK-NOT: is not a recognized feature for this target
|
|
|
|
; Make sure that the test was actually compiled.
|
|
; CHECK: li r3, 0
|
|
; CHECK-NEXT: blr
|
|
|