9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
54 lines
2.1 KiB
LLVM
54 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}store_v2i32_as_v4i16_align_4:
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; GCN: s_load_dwordx2
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; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
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define amdgpu_kernel void @store_v2i32_as_v4i16_align_4(ptr addrspace(3) align 4 %out, <2 x i32> %x) #0 {
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%x.bc = bitcast <2 x i32> %x to <4 x i16>
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store <4 x i16> %x.bc, ptr addrspace(3) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}store_v4i32_as_v8i16_align_4:
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; GCN: s_load_dwordx4
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; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
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; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
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define amdgpu_kernel void @store_v4i32_as_v8i16_align_4(ptr addrspace(3) align 4 %out, <4 x i32> %x) #0 {
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%x.bc = bitcast <4 x i32> %x to <8 x i16>
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store <8 x i16> %x.bc, ptr addrspace(3) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}store_v2i32_as_i64_align_4:
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; GCN: s_load_dwordx2
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; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
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define amdgpu_kernel void @store_v2i32_as_i64_align_4(ptr addrspace(3) align 4 %out, <2 x i32> %x) #0 {
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%x.bc = bitcast <2 x i32> %x to <4 x i16>
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store <4 x i16> %x.bc, ptr addrspace(3) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}store_v4i32_as_v2i64_align_4:
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; GCN: s_load_dwordx4
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; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
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; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
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define amdgpu_kernel void @store_v4i32_as_v2i64_align_4(ptr addrspace(3) align 4 %out, <4 x i32> %x) #0 {
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%x.bc = bitcast <4 x i32> %x to <2 x i64>
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store <2 x i64> %x.bc, ptr addrspace(3) %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}store_v4i16_as_v2i32_align_4:
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; GCN: s_load_dword s
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; GCN-NEXT: s_load_dwordx2 s
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; GCN-NOT: {{buffer|flat|global}}
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; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
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define amdgpu_kernel void @store_v4i16_as_v2i32_align_4(ptr addrspace(3) align 4 %out, <4 x i16> %x) #0 {
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%x.bc = bitcast <4 x i16> %x to <2 x i32>
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store <2 x i32> %x.bc, ptr addrspace(3) %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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