e9a3ea2218
This PR instruments the optimization passes in the SystemZ backend with calls to `MachineFunction::substituteDebugValuesForInst` where instruction substitutions are made to instructions that may compute tracked values. Tests are also added for each of the substitutions that were inserted. Details on the individual passes follow. ### systemz-copy-physregs When a copy targets an access register, we redirect the copy via an auxiliary register. This leads to the final result being written by a newly inserted SAR instruction, rather than the original MI, so we need to update the debug value tracking to account for this. ### systemz-long-branch This pass relaxes relative branch instructions based on the actual locations of blocks. Only one of the branch instructions qualifies for debug value tracking: BRCT, i.e. branch-relative-on-count, which subtracts 1 from a register and branches if the result is not zero. This is relaxed into an add-immediate and a conditional branch, so any `debug-instr-number` present must move to the add-immediate instruction. ### systemz-post-rewrite This pass replaces `LOCRMux` and `SELRMux` pseudoinstructions with either the real versions of those instructions, or with branching programs that implement the intent of the Pseudo. In all these cases, any `debug-instr-number` attached to the pseudo needs to be reallocated to the appropriate instruction in the result, either LOCR, SELR, or a COPY. ### systemz-elim-compare Similar to systemz-long-branch, for this pass, only few substitutions are necessary, since it mainly deals with conditional branch instructions. The only exceptiona are again branch-relative-on-count, as it modifies a counter as part of the instruction, as well as any of the load instructions that are affected.
33 lines
1.2 KiB
Python
33 lines
1.2 KiB
Python
# RUN: %python %s | llc -mtriple=s390x-linux-gnu -x mir --run-pass=systemz-long-branch \
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# RUN: | FileCheck %s
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# CHECK: debugValueSubstitutions:
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# CHECK: - { srcinst: 1, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
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# CHECK: - { srcinst: 1, srcop: 3, dstinst: 3, dstop: 3, subreg: 0 }
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# CHECK-NEXT: constants: []
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# CHECK: $r3l = AHI $r3l, -1
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# CHECK-NEXT: BRCL 14, 6, %bb.2
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print(" name: main")
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print(" alignment: 16")
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print(" tracksRegLiveness: true")
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print(" liveins: ")
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print(" - { reg: '$r1d', virtual-reg: '' }")
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print(" - { reg: '$r2d', virtual-reg: '' }")
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print(" - { reg: '$r3l', virtual-reg: '' }")
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print(" - { reg: '$r4l', virtual-reg: '' }")
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print(" debugValueSubstitutions: []")
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print(" body: |")
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print(" bb.0:")
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print(" liveins: $r3l, $r4l, $r2d, $r3d")
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print(" $r3l = BRCT $r3l, %bb.2, implicit-def $cc, debug-instr-number 1")
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print(" J %bb.1, debug-instr-number 2")
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print(" bb.1:")
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print(" liveins: $r1d, $r2d")
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for i in range(0, 8192):
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print(" $r1d = LGR $r2d")
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print(" $r2d = LGR $r1d")
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print(" Return implicit $r2d")
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print(" bb.2:")
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print(" liveins: $r4l")
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print(" Return implicit $r4l")
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