fbaf425b79
On AArch64, s128 types have to be split into s64 GPRs when passed as arguments. This change adds the generic support in call lowering for dealing with multiple registers, for incoming and outgoing args. Support for splitting for return types not yet implemented. Differential Revision: https://reviews.llvm.org/D66180 llvm-svn: 370822
432 lines
15 KiB
C++
432 lines
15 KiB
C++
//===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file This file implements the utility functions used by the GlobalISel
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/// pipeline.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/StackProtector.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/IR/Constants.h"
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#define DEBUG_TYPE "globalisel-utils"
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using namespace llvm;
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unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII,
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const RegisterBankInfo &RBI, unsigned Reg,
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const TargetRegisterClass &RegClass) {
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if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
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return MRI.createVirtualRegister(&RegClass);
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return Reg;
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}
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unsigned llvm::constrainOperandRegClass(
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const MachineFunction &MF, const TargetRegisterInfo &TRI,
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MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
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const RegisterBankInfo &RBI, MachineInstr &InsertPt,
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const TargetRegisterClass &RegClass, const MachineOperand &RegMO,
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unsigned OpIdx) {
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Register Reg = RegMO.getReg();
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// Assume physical registers are properly constrained.
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assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
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unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
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// If we created a new virtual register because the class is not compatible
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// then create a copy between the new and the old register.
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if (ConstrainedReg != Reg) {
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MachineBasicBlock::iterator InsertIt(&InsertPt);
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MachineBasicBlock &MBB = *InsertPt.getParent();
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if (RegMO.isUse()) {
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BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
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TII.get(TargetOpcode::COPY), ConstrainedReg)
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.addReg(Reg);
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} else {
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assert(RegMO.isDef() && "Must be a definition");
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BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
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TII.get(TargetOpcode::COPY), Reg)
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.addReg(ConstrainedReg);
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}
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}
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return ConstrainedReg;
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}
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unsigned llvm::constrainOperandRegClass(
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const MachineFunction &MF, const TargetRegisterInfo &TRI,
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MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
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const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
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const MachineOperand &RegMO, unsigned OpIdx) {
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Register Reg = RegMO.getReg();
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// Assume physical registers are properly constrained.
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assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
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const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
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// Some of the target independent instructions, like COPY, may not impose any
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// register class constraints on some of their operands: If it's a use, we can
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// skip constraining as the instruction defining the register would constrain
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// it.
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// We can't constrain unallocatable register classes, because we can't create
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// virtual registers for these classes, so we need to let targets handled this
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// case.
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if (RegClass && !RegClass->isAllocatable())
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RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI);
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if (!RegClass) {
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assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
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"Register class constraint is required unless either the "
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"instruction is target independent or the operand is a use");
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// FIXME: Just bailing out like this here could be not enough, unless we
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// expect the users of this function to do the right thing for PHIs and
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// COPY:
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// v1 = COPY v0
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// v2 = COPY v1
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// v1 here may end up not being constrained at all. Please notice that to
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// reproduce the issue we likely need a destination pattern of a selection
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// rule producing such extra copies, not just an input GMIR with them as
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// every existing target using selectImpl handles copies before calling it
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// and they never reach this function.
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return Reg;
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}
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return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass,
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RegMO, OpIdx);
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}
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bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
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const TargetInstrInfo &TII,
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const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) {
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assert(!isPreISelGenericOpcode(I.getOpcode()) &&
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"A selected instruction is expected");
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
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MachineOperand &MO = I.getOperand(OpI);
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// There's nothing to be done on non-register operands.
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if (!MO.isReg())
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continue;
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LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
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assert(MO.isReg() && "Unsupported non-reg operand");
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Register Reg = MO.getReg();
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// Physical registers don't need to be constrained.
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if (Register::isPhysicalRegister(Reg))
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continue;
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// Register operands with a value of 0 (e.g. predicate operands) don't need
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// to be constrained.
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if (Reg == 0)
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continue;
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// If the operand is a vreg, we should constrain its regclass, and only
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// insert COPYs if that's impossible.
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// constrainOperandRegClass does that for us.
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MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
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MO, OpI));
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// Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
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// done.
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if (MO.isUse()) {
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int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
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if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
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I.tieOperands(DefIdx, OpI);
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}
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}
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return true;
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}
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bool llvm::isTriviallyDead(const MachineInstr &MI,
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const MachineRegisterInfo &MRI) {
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// If we can move an instruction, we can remove it. Otherwise, it has
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// a side-effect of some sort.
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bool SawStore = false;
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if (!MI.isSafeToMove(/*AA=*/nullptr, SawStore) && !MI.isPHI())
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return false;
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// Instructions without side-effects are dead iff they only define dead vregs.
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for (auto &MO : MI.operands()) {
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if (!MO.isReg() || !MO.isDef())
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continue;
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Register Reg = MO.getReg();
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if (Register::isPhysicalRegister(Reg) || !MRI.use_nodbg_empty(Reg))
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return false;
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}
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return true;
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}
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void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
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MachineOptimizationRemarkEmitter &MORE,
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MachineOptimizationRemarkMissed &R) {
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MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
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// Print the function name explicitly if we don't have a debug location (which
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// makes the diagnostic less useful) or if we're going to emit a raw error.
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if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
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R << (" (in function: " + MF.getName() + ")").str();
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if (TPC.isGlobalISelAbortEnabled())
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report_fatal_error(R.getMsg());
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else
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MORE.emit(R);
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}
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void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
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MachineOptimizationRemarkEmitter &MORE,
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const char *PassName, StringRef Msg,
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const MachineInstr &MI) {
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MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ",
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MI.getDebugLoc(), MI.getParent());
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R << Msg;
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// Printing MI is expensive; only do it if expensive remarks are enabled.
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if (TPC.isGlobalISelAbortEnabled() || MORE.allowExtraAnalysis(PassName))
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R << ": " << ore::MNV("Inst", MI);
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reportGISelFailure(MF, TPC, MORE, R);
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}
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Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
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const MachineRegisterInfo &MRI) {
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Optional<ValueAndVReg> ValAndVReg =
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getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false);
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assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
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"Value found while looking through instrs");
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if (!ValAndVReg)
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return None;
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return ValAndVReg->Value;
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}
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Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough(
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unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs) {
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SmallVector<std::pair<unsigned, unsigned>, 4> SeenOpcodes;
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MachineInstr *MI;
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while ((MI = MRI.getVRegDef(VReg)) &&
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MI->getOpcode() != TargetOpcode::G_CONSTANT && LookThroughInstrs) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_TRUNC:
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case TargetOpcode::G_SEXT:
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case TargetOpcode::G_ZEXT:
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SeenOpcodes.push_back(std::make_pair(
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MI->getOpcode(),
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MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
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VReg = MI->getOperand(1).getReg();
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break;
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case TargetOpcode::COPY:
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VReg = MI->getOperand(1).getReg();
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if (Register::isPhysicalRegister(VReg))
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return None;
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break;
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case TargetOpcode::G_INTTOPTR:
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VReg = MI->getOperand(1).getReg();
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break;
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default:
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return None;
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}
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}
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if (!MI || MI->getOpcode() != TargetOpcode::G_CONSTANT ||
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(!MI->getOperand(1).isImm() && !MI->getOperand(1).isCImm()))
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return None;
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const MachineOperand &CstVal = MI->getOperand(1);
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unsigned BitWidth = MRI.getType(MI->getOperand(0).getReg()).getSizeInBits();
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APInt Val = CstVal.isImm() ? APInt(BitWidth, CstVal.getImm())
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: CstVal.getCImm()->getValue();
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assert(Val.getBitWidth() == BitWidth &&
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"Value bitwidth doesn't match definition type");
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while (!SeenOpcodes.empty()) {
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std::pair<unsigned, unsigned> OpcodeAndSize = SeenOpcodes.pop_back_val();
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switch (OpcodeAndSize.first) {
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case TargetOpcode::G_TRUNC:
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Val = Val.trunc(OpcodeAndSize.second);
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break;
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case TargetOpcode::G_SEXT:
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Val = Val.sext(OpcodeAndSize.second);
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break;
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case TargetOpcode::G_ZEXT:
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Val = Val.zext(OpcodeAndSize.second);
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break;
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}
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}
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if (Val.getBitWidth() > 64)
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return None;
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return ValueAndVReg{Val.getSExtValue(), VReg};
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}
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const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
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const MachineRegisterInfo &MRI) {
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MachineInstr *MI = MRI.getVRegDef(VReg);
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if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
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return nullptr;
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return MI->getOperand(1).getFPImm();
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}
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llvm::MachineInstr *llvm::getDefIgnoringCopies(Register Reg,
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const MachineRegisterInfo &MRI) {
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auto *DefMI = MRI.getVRegDef(Reg);
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auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
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if (!DstTy.isValid())
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return nullptr;
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while (DefMI->getOpcode() == TargetOpcode::COPY) {
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Register SrcReg = DefMI->getOperand(1).getReg();
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auto SrcTy = MRI.getType(SrcReg);
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if (!SrcTy.isValid() || SrcTy != DstTy)
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break;
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DefMI = MRI.getVRegDef(SrcReg);
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}
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return DefMI;
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}
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llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg,
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const MachineRegisterInfo &MRI) {
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MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI);
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return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr;
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}
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APFloat llvm::getAPFloatFromSize(double Val, unsigned Size) {
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if (Size == 32)
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return APFloat(float(Val));
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if (Size == 64)
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return APFloat(Val);
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if (Size != 16)
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llvm_unreachable("Unsupported FPConstant size");
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bool Ignored;
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APFloat APF(Val);
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APF.convert(APFloat::IEEEhalf(), APFloat::rmNearestTiesToEven, &Ignored);
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return APF;
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}
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Optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode, const unsigned Op1,
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const unsigned Op2,
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const MachineRegisterInfo &MRI) {
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auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI);
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auto MaybeOp2Cst = getConstantVRegVal(Op2, MRI);
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if (MaybeOp1Cst && MaybeOp2Cst) {
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LLT Ty = MRI.getType(Op1);
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APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true);
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APInt C2(Ty.getSizeInBits(), *MaybeOp2Cst, true);
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switch (Opcode) {
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default:
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break;
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case TargetOpcode::G_ADD:
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return C1 + C2;
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case TargetOpcode::G_AND:
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return C1 & C2;
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case TargetOpcode::G_ASHR:
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return C1.ashr(C2);
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case TargetOpcode::G_LSHR:
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return C1.lshr(C2);
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case TargetOpcode::G_MUL:
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return C1 * C2;
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case TargetOpcode::G_OR:
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return C1 | C2;
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case TargetOpcode::G_SHL:
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return C1 << C2;
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case TargetOpcode::G_SUB:
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return C1 - C2;
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case TargetOpcode::G_XOR:
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return C1 ^ C2;
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case TargetOpcode::G_UDIV:
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if (!C2.getBoolValue())
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break;
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return C1.udiv(C2);
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case TargetOpcode::G_SDIV:
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if (!C2.getBoolValue())
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break;
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return C1.sdiv(C2);
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case TargetOpcode::G_UREM:
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if (!C2.getBoolValue())
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break;
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return C1.urem(C2);
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case TargetOpcode::G_SREM:
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if (!C2.getBoolValue())
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break;
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return C1.srem(C2);
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}
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}
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return None;
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}
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bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
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bool SNaN) {
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const MachineInstr *DefMI = MRI.getVRegDef(Val);
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if (!DefMI)
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return false;
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if (DefMI->getFlag(MachineInstr::FmNoNans))
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return true;
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if (SNaN) {
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// FP operations quiet. For now, just handle the ones inserted during
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// legalization.
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switch (DefMI->getOpcode()) {
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case TargetOpcode::G_FPEXT:
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case TargetOpcode::G_FPTRUNC:
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case TargetOpcode::G_FCANONICALIZE:
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return true;
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default:
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return false;
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}
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}
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return false;
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}
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Optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode, const unsigned Op1,
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uint64_t Imm,
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const MachineRegisterInfo &MRI) {
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auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI);
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if (MaybeOp1Cst) {
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LLT Ty = MRI.getType(Op1);
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APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true);
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switch (Opcode) {
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default:
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break;
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case TargetOpcode::G_SEXT_INREG:
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return C1.trunc(Imm).sext(C1.getBitWidth());
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}
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}
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return None;
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}
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void llvm::getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU) {
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AU.addPreserved<StackProtector>();
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}
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MVT llvm::getMVTForLLT(LLT Ty) {
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if (!Ty.isVector())
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return MVT::getIntegerVT(Ty.getSizeInBits());
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return MVT::getVectorVT(
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MVT::getIntegerVT(Ty.getElementType().getSizeInBits()),
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Ty.getNumElements());
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}
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LLT llvm::getLLTForMVT(MVT Ty) {
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if (!Ty.isVector())
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return LLT::scalar(Ty.getSizeInBits());
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return LLT::vector(Ty.getVectorNumElements(),
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Ty.getVectorElementType().getSizeInBits());
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}
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