2910184936
Copied directly from the IR version. Most of the testcases I've added for this are somewhat problematic because they really end up testing the yet to be implemented version for MUL_I24/MUL_U24. llvm-svn: 370099
160 lines
5.0 KiB
LLVM
160 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - -amdgpu-codegenprepare-mul24=0 < %s | FileCheck -check-prefix=GFX9 %s
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define i16 @num_sign_bits_mul_i48_0(i8 %X, i8 %Y, i8 %Z, i8 %W) {
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; GFX9-LABEL: num_sign_bits_mul_i48_0:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mul_i32_i24_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
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; GFX9-NEXT: v_mul_i32_i24_sdwa v1, sext(v2), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
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; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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%A = sext i8 %X to i48
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%B = sext i8 %Y to i48
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%C = sext i8 %Z to i48
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%D = sext i8 %W to i48
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%mul0 = mul i48 %A, %B
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%mul1 = mul i48 %C, %D
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%mul2 = mul i48 %mul0, %mul1
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%trunc = trunc i48 %mul2 to i16
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ret i16 %trunc
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}
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define i16 @num_sign_bits_mul_i48_1(i8 %X, i8 %Y, i8 %Z, i8 %W) {
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; GFX9-LABEL: num_sign_bits_mul_i48_1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mul_i32_i24_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
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; GFX9-NEXT: v_mul_i32_i24_sdwa v2, sext(v2), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
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; GFX9-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v2
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; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v2
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; GFX9-NEXT: v_lshrrev_b64 v[0:1], 24, v[0:1]
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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%A = sext i8 %X to i48
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%B = sext i8 %Y to i48
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%C = sext i8 %Z to i48
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%D = sext i8 %W to i48
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%mul0 = mul i48 %A, %B
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%mul1 = mul i48 %C, %D
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%mul2 = mul i48 %mul0, %mul1
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%ashr = ashr i48 %mul2, 24
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%trunc = trunc i48 %ashr to i16
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ret i16 %trunc
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}
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define i32 @num_sign_bits_mul_i32_7(i32 %x, i32 %y, i32 %z, i32 %w) {
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; GFX9-LABEL: num_sign_bits_mul_i32_7:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 25
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; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 25
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; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 25
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; GFX9-NEXT: v_bfe_i32 v3, v3, 0, 25
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; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1
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; GFX9-NEXT: v_mul_lo_u32 v1, v2, v3
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; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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%x.shl = shl i32 %x, 7
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%x.bits = ashr i32 %x.shl, 7
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%y.shl = shl i32 %y, 7
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%y.bits = ashr i32 %y.shl, 7
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%z.shl = shl i32 %z, 7
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%z.bits = ashr i32 %z.shl, 7
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%w.shl = shl i32 %w, 7
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%w.bits = ashr i32 %w.shl, 7
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%mul0 = mul i32 %x.bits, %y.bits
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%mul1 = mul i32 %z.bits, %w.bits
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%mul2 = mul i32 %mul0, %mul1
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ret i32 %mul2
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}
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define i32 @num_sign_bits_mul_i32_8(i32 %x, i32 %y, i32 %z, i32 %w) {
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; GFX9-LABEL: num_sign_bits_mul_i32_8:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
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; GFX9-NEXT: v_mul_i32_i24_e32 v1, v2, v3
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; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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%x.shl = shl i32 %x, 8
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%x.bits = ashr i32 %x.shl, 8
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%y.shl = shl i32 %y, 8
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%y.bits = ashr i32 %y.shl, 8
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%z.shl = shl i32 %z, 8
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%z.bits = ashr i32 %z.shl, 8
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%w.shl = shl i32 %w, 8
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%w.bits = ashr i32 %w.shl, 8
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%mul0 = mul i32 %x.bits, %y.bits
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%mul1 = mul i32 %z.bits, %w.bits
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%mul2 = mul i32 %mul0, %mul1
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ret i32 %mul2
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}
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define i32 @num_sign_bits_mul_i32_9(i32 %x, i32 %y, i32 %z, i32 %w) {
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; GFX9-LABEL: num_sign_bits_mul_i32_9:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 23
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; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 23
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; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 23
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; GFX9-NEXT: v_bfe_i32 v3, v3, 0, 23
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; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
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; GFX9-NEXT: v_mul_i32_i24_e32 v1, v2, v3
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; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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%x.shl = shl i32 %x, 9
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%x.bits = ashr i32 %x.shl, 9
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%y.shl = shl i32 %y, 9
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%y.bits = ashr i32 %y.shl, 9
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%z.shl = shl i32 %z, 9
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%z.bits = ashr i32 %z.shl, 9
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%w.shl = shl i32 %w, 9
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%w.bits = ashr i32 %w.shl, 9
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%mul0 = mul i32 %x.bits, %y.bits
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%mul1 = mul i32 %z.bits, %w.bits
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%mul2 = mul i32 %mul0, %mul1
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ret i32 %mul2
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}
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define i32 @num_sign_bits_mul_i32_10(i32 %x, i32 %y, i32 %z, i32 %w) {
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; GFX9-LABEL: num_sign_bits_mul_i32_10:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 22
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; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 22
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; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 22
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; GFX9-NEXT: v_bfe_i32 v3, v3, 0, 22
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; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
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; GFX9-NEXT: v_mul_i32_i24_e32 v1, v2, v3
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; GFX9-NEXT: v_mul_lo_u32 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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%x.shl = shl i32 %x, 10
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%x.bits = ashr i32 %x.shl, 10
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%y.shl = shl i32 %y, 10
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%y.bits = ashr i32 %y.shl, 10
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%z.shl = shl i32 %z, 10
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%z.bits = ashr i32 %z.shl, 10
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%w.shl = shl i32 %w, 10
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%w.bits = ashr i32 %w.shl, 10
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%mul0 = mul i32 %x.bits, %y.bits
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%mul1 = mul i32 %z.bits, %w.bits
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%mul2 = mul i32 %mul0, %mul1
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ret i32 %mul2
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}
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