"Divergence driven ISel. Assign register class for cross block values
according to the divergence."
that discovered the design flaw leading to several issues that
required to be solved before.
This change reverts AMDGPU specific changes and keeps common part
unaffected.
llvm-svn: 362749
70 lines
1.7 KiB
LLVM
70 lines
1.7 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s
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; Test a simple uniform loop that lives inside non-uniform control flow.
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; CHECK-LABEL: {{^}}test1:
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; CHECK: v_cmp_ne_u32_e32 vcc, 0
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; CHECK: s_and_saveexec_b64
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; CHECK-NEXT: ; mask branch
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; CHECK-NEXT: s_cbranch_execz BB{{[0-9]+_[0-9]+}}
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; CHECK-NEXT: BB{{[0-9]+_[0-9]+}}: ; %loop_body.preheader
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; CHECK: [[LOOP_BODY_LABEL:BB[0-9]+_[0-9]+]]:
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; CHECK: s_cbranch_vccz [[LOOP_BODY_LABEL]]
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; CHECK: s_endpgm
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define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <2 x i32> %addr.base, i32 %y, i32 %p) {
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main_body:
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%cc = icmp eq i32 %p, 0
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br i1 %cc, label %out, label %loop_body
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loop_body:
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%counter = phi i32 [ 0, %main_body ], [ %incr, %loop_body ]
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; Prevent the loop from being optimized out
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call void asm sideeffect "", "" ()
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%incr = add i32 %counter, 1
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%lc = icmp sge i32 %incr, 1000
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br i1 %lc, label %out, label %loop_body
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out:
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ret void
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}
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; CHECK-LABEL: {{^}}test2:
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; CHECK: s_and_saveexec_b64
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; CHECK-NEXT: ; mask branch
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; CHECK-NEXT: s_cbranch_execz
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define amdgpu_kernel void @test2(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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main_body:
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%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
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%cc = icmp eq i32 %tid, 0
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br i1 %cc, label %done1, label %if
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if:
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%cmp = icmp eq i32 %a, 0
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br i1 %cmp, label %done0, label %loop_body
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loop_body:
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%counter = phi i32 [ 0, %if ], [0, %done0], [ %incr, %loop_body ]
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; Prevent the loop from being optimized out
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call void asm sideeffect "", "" ()
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%incr = add i32 %counter, 1
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%lc = icmp sge i32 %incr, 1000
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br i1 %lc, label %done1, label %loop_body
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done0:
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%cmp0 = icmp eq i32 %b, 0
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br i1 %cmp0, label %done1, label %loop_body
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done1:
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #1 = { nounwind readonly }
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