1ff9553057
MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices. Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used. Differential Revision: https://reviews.llvm.org/D67327 llvm-svn: 372114
186 lines
6.3 KiB
YAML
186 lines
6.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -o - %s -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s
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---
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name: func0
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tracksRegLiveness: true
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stack:
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- { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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local-offset: -16, debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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body: |
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bb.0:
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; CHECK-LABEL: name: func0
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; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
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; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
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; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
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; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
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; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
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; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
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; CHECK: $sp = frame-setup tSUBspi $sp, 5, 14, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 56
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; CHECK: $r0 = IMPLICIT_DEF
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; CHECK: $r1 = IMPLICIT_DEF
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; CHECK: $r2 = IMPLICIT_DEF
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; CHECK: $r3 = IMPLICIT_DEF
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; CHECK: $r4 = IMPLICIT_DEF
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; CHECK: $r5 = IMPLICIT_DEF
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; CHECK: $r6 = IMPLICIT_DEF
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; CHECK: $r7 = IMPLICIT_DEF
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; CHECK: $r8 = IMPLICIT_DEF
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; CHECK: $r9 = IMPLICIT_DEF
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; CHECK: $r10 = IMPLICIT_DEF
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; CHECK: $r11 = IMPLICIT_DEF
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; CHECK: $r12 = IMPLICIT_DEF
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; CHECK: $lr = IMPLICIT_DEF
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; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.1)
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; CHECK: $r0 = tMOVr killed $sp, 14, $noreg
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; CHECK: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load 4 from %stack.0 + 12)
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; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.1)
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; CHECK: KILL $r0
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; CHECK: KILL $r1
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; CHECK: KILL $r2
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; CHECK: KILL $r3
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; CHECK: KILL $r4
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; CHECK: KILL $r5
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; CHECK: KILL $r6
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; CHECK: KILL $r7
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; CHECK: KILL $r8
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; CHECK: KILL $r9
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; CHECK: KILL $r10
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; CHECK: KILL $r11
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; CHECK: KILL $r12
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; CHECK: KILL $lr
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$r0 = IMPLICIT_DEF
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$r1 = IMPLICIT_DEF
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$r2 = IMPLICIT_DEF
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$r3 = IMPLICIT_DEF
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$r4 = IMPLICIT_DEF
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$r5 = IMPLICIT_DEF
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$r6 = IMPLICIT_DEF
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$r7 = IMPLICIT_DEF
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$r8 = IMPLICIT_DEF
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$r9 = IMPLICIT_DEF
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$r10 = IMPLICIT_DEF
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$r11 = IMPLICIT_DEF
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$r12 = IMPLICIT_DEF
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$lr = IMPLICIT_DEF
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renamable $q2 = MVE_VLDRBU32 %stack.0, 12, 0, $noreg :: (load 4 from %stack.0 + 12)
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KILL $r0
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KILL $r1
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KILL $r2
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KILL $r3
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KILL $r4
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KILL $r5
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KILL $r6
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KILL $r7
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KILL $r8
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KILL $r9
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KILL $r10
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KILL $r11
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KILL $r12
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KILL $lr
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...
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---
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name: func1
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tracksRegLiveness: true
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stack:
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- { id: 0, name: '', type: default, offset: 0, size: 16, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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local-offset: -1200, debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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- { id: 1, name: '', type: default, offset: 0, size: 1200, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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local-offset: -1200, debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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body: |
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bb.0:
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; CHECK-LABEL: name: func1
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; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr
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; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8
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; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12
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; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -16
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; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -20
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -24
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; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36
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; CHECK: $sp = frame-setup t2SUBri killed $sp, 1216, 14, $noreg, $noreg
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; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1256
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; CHECK: $r0 = IMPLICIT_DEF
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; CHECK: $r1 = IMPLICIT_DEF
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; CHECK: $r2 = IMPLICIT_DEF
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; CHECK: $r3 = IMPLICIT_DEF
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; CHECK: $r4 = IMPLICIT_DEF
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; CHECK: $r5 = IMPLICIT_DEF
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; CHECK: $r6 = IMPLICIT_DEF
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; CHECK: $r7 = IMPLICIT_DEF
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; CHECK: $r8 = IMPLICIT_DEF
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; CHECK: $r9 = IMPLICIT_DEF
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; CHECK: $r10 = IMPLICIT_DEF
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; CHECK: $r11 = IMPLICIT_DEF
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; CHECK: $r12 = IMPLICIT_DEF
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; CHECK: $lr = IMPLICIT_DEF
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; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2)
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; CHECK: $r0 = t2ADDri killed $sp, 1152, 14, $noreg, $noreg
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; CHECK: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load 4 from %stack.0)
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; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2)
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; CHECK: KILL $r0
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; CHECK: KILL $r1
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; CHECK: KILL $r2
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; CHECK: KILL $r3
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; CHECK: KILL $r4
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; CHECK: KILL $r5
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; CHECK: KILL $r6
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; CHECK: KILL $r7
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; CHECK: KILL $r8
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; CHECK: KILL $r9
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; CHECK: KILL $r10
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; CHECK: KILL $r11
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; CHECK: KILL $r12
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; CHECK: KILL $lr
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$r0 = IMPLICIT_DEF
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$r1 = IMPLICIT_DEF
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$r2 = IMPLICIT_DEF
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$r3 = IMPLICIT_DEF
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$r4 = IMPLICIT_DEF
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$r5 = IMPLICIT_DEF
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$r6 = IMPLICIT_DEF
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$r7 = IMPLICIT_DEF
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$r8 = IMPLICIT_DEF
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$r9 = IMPLICIT_DEF
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$r10 = IMPLICIT_DEF
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$r11 = IMPLICIT_DEF
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$r12 = IMPLICIT_DEF
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$lr = IMPLICIT_DEF
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renamable $q2 = MVE_VLDRBU8 %stack.0, 0, 0, $noreg :: (load 4 from %stack.0)
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KILL $r0
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KILL $r1
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KILL $r2
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KILL $r3
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KILL $r4
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KILL $r5
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KILL $r6
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KILL $r7
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KILL $r8
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KILL $r9
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KILL $r10
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KILL $r11
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KILL $r12
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KILL $lr
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...
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