Sergey Kachkov ca0b4d58ea [libunwind][RISCV] Support reading of VLENB CSR register ...

Support reading of VLENB (vector byte length) control register, that can be
required for correct unwinding of RVV objects on stack.

Differential Revision: https://reviews.llvm.org/D136264

2022-12-06 11:48:54 +03:00

..

configs

[runtimes] Remove all traces of the legacy testing configuration system

2022-09-30 15:03:33 -04:00

alignment.compile.pass.cpp

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bad_unwind_info.pass.cpp

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CMakeLists.txt

Revert "[CMake] Use LLVM_TARGET_TRIPLE in runtimes"

2022-12-05 22:20:51 +00:00

floatregister.pass.cpp

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forceunwind.pass.cpp

[libunwind] undef NDEBUG for assert.h in tests.

2022-08-04 19:55:40 -07:00

frameheadercache_test.pass.cpp

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libunwind_01.pass.cpp

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libunwind_02.pass.cpp

[libunwind] undef NDEBUG for assert.h in tests.

2022-08-04 19:55:40 -07:00

lit.cfg.py

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remember_state_leak.pass.sh.s

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signal_frame.pass.cpp

[libunwind] undef NDEBUG for assert.h in tests.

2022-08-04 19:55:40 -07:00

signal_unwind.pass.cpp

[libunwind] undef NDEBUG for assert.h in tests.

2022-08-04 19:55:40 -07:00

unw_getcontext.pass.cpp

[libunwind] undef NDEBUG for assert.h in tests.

2022-08-04 19:55:40 -07:00

unwind_leaffunction.pass.cpp

[libunwind] Fixed a number of typos

2022-08-20 18:09:03 -07:00

unwind_scalable_vectors.pass.cpp

[libunwind][RISCV] Support reading of VLENB CSR register

2022-12-06 11:48:54 +03:00