Brendan Dahl 4ebe9bba59 [WebAssembly] Implement prototype f16x8.extract_lane instruction. (#93272) ...

Specified at:

29a9b9462c/proposals/half-precision/Overview.md

Note: the current spec has f16x8.extract_lane as opcode 0x124, but this
is incorrect and will be changed to 0x121 soon.

2024-05-24 08:31:07 -07:00

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AArch64

Revert "Run ObjCContractPass in Default Codegen Pipeline (#92331)"

2024-05-24 08:14:26 +02:00

AMDGPU

Revert "Run ObjCContractPass in Default Codegen Pipeline (#92331)"

2024-05-24 08:14:26 +02:00

ARC

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ARM

Revert "Run ObjCContractPass in Default Codegen Pipeline (#92331)"

2024-05-24 08:14:26 +02:00

AVR

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BPF

[BPF] report Invalid usage of the XADD return value" elegantly (#92742)

2024-05-21 01:57:56 +08:00

CSKY

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DirectX

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Generic

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Hexagon

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Inputs

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Lanai

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LoongArch

Revert "Run ObjCContractPass in Default Codegen Pipeline (#92331)"

2024-05-24 08:14:26 +02:00

M68k

Revert "Run ObjCContractPass in Default Codegen Pipeline (#92331)"

2024-05-24 08:14:26 +02:00

Mips

MIPS: Fix llvm.{min,max}num for R6 (#93125)

2024-05-23 22:27:17 +08:00

MIR

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MLRegAlloc

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MSP430

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NVPTX

NVPTX: fix test failures under ptxas-12.0.

2024-05-20 23:09:26 -04:00

PowerPC

Revert "Run ObjCContractPass in Default Codegen Pipeline (#92331)"

2024-05-24 08:14:26 +02:00

RISCV

Revert "Run ObjCContractPass in Default Codegen Pipeline (#92331)"

2024-05-24 08:14:26 +02:00

SPARC

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SPIRV

[SPIR-V] Enable spirv-val in SPV_KHR_shader_clock test (#93292)

2024-05-24 15:30:44 +02:00

SystemZ

SystemZ: Use REG_SEQUENCE for PAIR128 (#90640)

2024-05-17 13:16:34 +02:00

Thumb

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Thumb2

[SDAG] Improve SimplifyDemandedBits for mul (#90034)

2024-05-22 22:43:10 +08:00

VE

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WebAssembly

[WebAssembly] Implement prototype f16x8.extract_lane instruction. (#93272)

2024-05-24 08:31:07 -07:00

WinCFGuard

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WinEH

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X86

[X86] combineBitcastToBoolVector - add XOR + Constant handling, match existing BITCASTs and limit recursion depth

2024-05-24 16:30:23 +01:00

XCore

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Xtensa

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