ac1ffd3cac
Rework the change to prevent build failures. NFCI. The failing code was submitted ascf7a8305a2and reverted via8bd65e535f. The rework in this new commit prevents failures like the following: FAILED: tools/clang/lib/Basic/CMakeFiles/obj.clangBasic.dir/Targets/RISCV.cpp.o /usr/bin/c++ [bunch of non interesting stuff] -c <path-to>/llvm-project/clang/lib/Basic/Targets/RISCV.cpp In file included from <path-to>/llvm-project/clang/lib/Basic/Targets/RISCV.cpp:19: <path-to>/llvm-project/llvm/include/llvm/TargetParser/RISCVTargetParser.h:29:10: fatal error: llvm/TargetParser/RISCVTargetParserDef.inc: No such file or directory 29 | #include "llvm/TargetParser/RISCVTargetParserDef.inc" | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ These failures happen because the library LLVMTargetParser depends on RISCVTargetParserTableGen, which is a tablegen target that generates the list of CPUs in llvm/TargetParser/RISCVTargetParserDef.inc. This *.inc file is included by the public header file llvm/TargetParser/RISCVTargetParser.h. The header file llvm/TargetParser/RISCVTargetParser.h is also used in components (clangDriver and clangBasic) that link into LLVMTargetParser, but on some configurations such components might end up being built before TargetParser is ready. The fix is to make sure that clangDriver and clangBasic depend on the tablegen target RISCVTargetParserTableGen, which generates the .inc file whether or not LLVMTargetParser is ready. WRT the original patch at https://reviews.llvm.org/D137517, this commit is just adding RISCVTargetParserTableGen in the DEPENDS list of clangDriver and clangBasic.
105 lines
3.3 KiB
C++
105 lines
3.3 KiB
C++
//===-- RISCVTargetParser.cpp - Parser for target features ------*- C++ -*-===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file implements a target parser to recognise hardware features
|
|
// FOR RISC-V CPUS.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/TargetParser/RISCVTargetParser.h"
|
|
#include "llvm/ADT/SmallVector.h"
|
|
#include "llvm/ADT/StringSwitch.h"
|
|
|
|
namespace llvm {
|
|
namespace RISCV {
|
|
|
|
struct CPUInfo {
|
|
StringLiteral Name;
|
|
CPUKind Kind;
|
|
unsigned Features;
|
|
StringLiteral DefaultMarch;
|
|
bool is64Bit() const { return (Features & FK_64BIT); }
|
|
};
|
|
|
|
constexpr CPUInfo RISCVCPUInfo[] = {
|
|
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) \
|
|
{NAME, CK_##ENUM, FEATURES, DEFAULT_MARCH},
|
|
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
|
|
};
|
|
|
|
bool checkCPUKind(CPUKind Kind, bool IsRV64) {
|
|
if (Kind == CK_INVALID)
|
|
return false;
|
|
return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
|
|
}
|
|
|
|
bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) {
|
|
if (Kind == CK_INVALID)
|
|
return false;
|
|
#define TUNE_PROC(ENUM, NAME) \
|
|
if (Kind == CK_##ENUM) \
|
|
return true;
|
|
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
|
|
return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
|
|
}
|
|
|
|
CPUKind parseCPUKind(StringRef CPU) {
|
|
return llvm::StringSwitch<CPUKind>(CPU)
|
|
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
|
|
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
|
|
.Default(CK_INVALID);
|
|
}
|
|
|
|
CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) {
|
|
return llvm::StringSwitch<CPUKind>(TuneCPU)
|
|
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
|
|
#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
|
|
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
|
|
.Default(CK_INVALID);
|
|
}
|
|
|
|
StringRef getMArchFromMcpu(StringRef CPU) {
|
|
CPUKind Kind = parseCPUKind(CPU);
|
|
return RISCVCPUInfo[static_cast<unsigned>(Kind)].DefaultMarch;
|
|
}
|
|
|
|
void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
|
|
for (const auto &C : RISCVCPUInfo) {
|
|
if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
|
|
Values.emplace_back(C.Name);
|
|
}
|
|
}
|
|
|
|
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
|
|
for (const auto &C : RISCVCPUInfo) {
|
|
if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
|
|
Values.emplace_back(C.Name);
|
|
}
|
|
#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
|
|
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
|
|
}
|
|
|
|
// Get all features except standard extension feature
|
|
bool getCPUFeaturesExceptStdExt(CPUKind Kind,
|
|
std::vector<StringRef> &Features) {
|
|
unsigned CPUFeatures = RISCVCPUInfo[static_cast<unsigned>(Kind)].Features;
|
|
|
|
if (CPUFeatures == FK_INVALID)
|
|
return false;
|
|
|
|
if (CPUFeatures & FK_64BIT)
|
|
Features.push_back("+64bit");
|
|
else
|
|
Features.push_back("-64bit");
|
|
|
|
return true;
|
|
}
|
|
|
|
} // namespace RISCV
|
|
} // namespace llvm
|