9d9a86535e
Commit r323512 introduced an optimisation in LowerReturn for half-precision return values. A missing check caused a crash when the return value is "undef" (i.e. a node that has no operands). Differential Revision: https://reviews.llvm.org/D42743 llvm-svn: 323968
82 lines
3.1 KiB
LLVM
82 lines
3.1 KiB
LLVM
; SOFT:
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; RUN: llc < %s -mtriple=arm-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
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; SOFTFP:
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp3 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-VFP3
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp4 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16
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; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FULLFP16
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; HARD:
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; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp3 | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-VFP3
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; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp4 | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FP16
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; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FULLFP16
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define float @RetValBug(float %A.coerce) local_unnamed_addr {
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entry:
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ret float undef
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; This expression is optimised away due to the undef value. Check that
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; LowerReturn can handle undef nodes (i.e. nodes which do not have any
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; operands) when FullFP16 is enabled.
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;
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; CHECK-LABEL: RetValBug:
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; CHECK-HARDFP-FULLFP16: mov pc, lr
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}
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define float @Add(float %a.coerce, float %b.coerce) local_unnamed_addr {
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entry:
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%0 = bitcast float %a.coerce to i32
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%tmp.0.extract.trunc = trunc i32 %0 to i16
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%1 = bitcast i16 %tmp.0.extract.trunc to half
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%2 = bitcast float %b.coerce to i32
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%tmp1.0.extract.trunc = trunc i32 %2 to i16
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%3 = bitcast i16 %tmp1.0.extract.trunc to half
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%add = fadd half %1, %3
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%4 = bitcast half %add to i16
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%tmp4.0.insert.ext = zext i16 %4 to i32
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%5 = bitcast i32 %tmp4.0.insert.ext to float
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ret float %5
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; CHECK-LABEL: Add:
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; CHECK-SOFT: bl __aeabi_h2f
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; CHECK-SOFT: bl __aeabi_h2f
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; CHECK-SOFT: bl __aeabi_fadd
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; CHECK-SOFT: bl __aeabi_f2h
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; CHECK-SOFTFP-VFP3: bl __aeabi_h2f
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; CHECK-SOFTFP-VFP3: bl __aeabi_h2f
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; CHECK-SOFTFP-VFP3: vadd.f32
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; CHECK-SOFTFP-VFP3: bl __aeabi_f2h
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; CHECK-SOFTFP-FP16: vmov [[S2:s[0-9]]], r1
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; CHECK-SOFTFP-FP16: vmov [[S0:s[0-9]]], r0
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; CHECK-SOFTFP-FP16: vcvtb.f32.f16 [[S2]], [[S2]]
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; CHECK-SOFTFP-FP16: vcvtb.f32.f16 [[S0]], [[S0]]
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; CHECK-SOFTFP-FP16: vadd.f32 [[S0]], [[S0]], [[S2]]
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; CHECK-SOFTFP-FP16: vcvtb.f16.f32 [[S0]], [[S0]]
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; CHECK-SOFTFP-FP16: vmov r0, s0
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; CHECK-SOFTFP-FULLFP16: vmov.f16 [[S0:s[0-9]]], r1
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; CHECK-SOFTFP-FULLFP16: vmov.f16 [[S2:s[0-9]]], r0
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; CHECK-SOFTFP-FULLFP16: vadd.f16 [[S0]], [[S2]], [[S0]]
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; CHECK-SOFTFP-FULLFP16-NEXT: vmov.f16 r0, s0
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; CHECK-SOFTFP-FULLFP16-NEXT: mov pc, lr
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; CHECK-HARDFP-VFP3: vmov r{{.}}, s0
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; CHECK-HARDFP-VFP3: vmov{{.*}}, s1
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; CHECK-HARDFP-VFP3: bl __aeabi_h2f
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; CHECK-HARDFP-VFP3: bl __aeabi_h2f
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; CHECK-HARDFP-VFP3: vadd.f32
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; CHECK-HARDFP-VFP3: bl __aeabi_f2h
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; CHECK-HARDFP-VFP3: vmov s0, r0
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; CHECK-HARDFP-FP16: vcvtb.f32.f16 [[S2:s[0-9]]], s1
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; CHECK-HARDFP-FP16: vcvtb.f32.f16 [[S0:s[0-9]]], s0
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; CHECK-HARDFP-FP16: vadd.f32 [[S0]], [[S0]], [[S2]]
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; CHECK-HARDFP-FP16: vcvtb.f16.f32 [[S0]], [[S0]]
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; CHECK-HARDFP-FULLFP16: vadd.f16 s0, s0, s1
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; CHECK-HARDFP-FULLFP16-NEXT: mov pc, lr
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}
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