94503c7bc3
Summary: This change extends MachineCopyPropagation to do COPY source forwarding and adds an additional run of the pass to the default pass pipeline just after register allocation. This version of this patch uses the newly added MachineOperand::isRenamable bit to avoid forwarding registers is such a way as to violate constraints that aren't captured in the Machine IR (e.g. ABI or ISA constraints). This change is a continuation of the work started in D30751. Reviewers: qcolombet, javed.absar, MatzeB, jonpa, tstellar Subscribers: tpr, mgorny, mcrosier, nhaehnle, nemanjai, jyknight, hfinkel, arsenm, inouehrs, eraman, sdardis, guyblank, fedor.sergeev, aheejin, dschuff, jfb, myatsina, llvm-commits Differential Revision: https://reviews.llvm.org/D41835 llvm-svn: 323991
240 lines
8.0 KiB
LLVM
240 lines
8.0 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse2 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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declare float @fmaxf(float, float)
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declare double @fmax(double, double)
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declare x86_fp80 @fmaxl(x86_fp80, x86_fp80)
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declare float @llvm.maxnum.f32(float, float)
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declare double @llvm.maxnum.f64(double, double)
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declare x86_fp80 @llvm.maxnum.f80(x86_fp80, x86_fp80)
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declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
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declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>)
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declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>)
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declare <4 x double> @llvm.maxnum.v4f64(<4 x double>, <4 x double>)
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declare <8 x double> @llvm.maxnum.v8f64(<8 x double>, <8 x double>)
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; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.
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; CHECK-LABEL: @test_fmaxf
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; SSE: movaps %xmm0, %xmm2
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; SSE-NEXT: cmpunordss %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: maxss %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm1, %xmm2
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; SSE-NEXT: orps %xmm3, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vmaxss %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define float @test_fmaxf(float %x, float %y) {
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%z = call float @fmaxf(float %x, float %y) readnone
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ret float %z
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}
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; CHECK-LABEL: @test_fmaxf_minsize
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; CHECK: jmp fmaxf
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define float @test_fmaxf_minsize(float %x, float %y) minsize {
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%z = call float @fmaxf(float %x, float %y) readnone
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ret float %z
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}
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; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.
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; CHECK-LABEL: @test_fmax
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; SSE: movapd %xmm0, %xmm2
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; SSE-NEXT: cmpunordsd %xmm0, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm3
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: maxsd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm1, %xmm2
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; SSE-NEXT: orpd %xmm3, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vmaxsd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define double @test_fmax(double %x, double %y) {
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%z = call double @fmax(double %x, double %y) readnone
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ret double %z
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}
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; CHECK-LABEL: @test_fmaxl
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; CHECK: callq fmaxl
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define x86_fp80 @test_fmaxl(x86_fp80 %x, x86_fp80 %y) {
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%z = call x86_fp80 @fmaxl(x86_fp80 %x, x86_fp80 %y) readnone
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ret x86_fp80 %z
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}
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; CHECK-LABEL: @test_intrinsic_fmaxf
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; SSE: movaps %xmm0, %xmm2
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; SSE-NEXT: cmpunordss %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: maxss %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm1, %xmm2
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; SSE-NEXT: orps %xmm3, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vmaxss %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define float @test_intrinsic_fmaxf(float %x, float %y) {
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%z = call float @llvm.maxnum.f32(float %x, float %y) readnone
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ret float %z
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}
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; CHECK-LABEL: @test_intrinsic_fmax
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; SSE: movapd %xmm0, %xmm2
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; SSE-NEXT: cmpunordsd %xmm0, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm3
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: maxsd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm1, %xmm2
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; SSE-NEXT: orpd %xmm3, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vmaxsd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define double @test_intrinsic_fmax(double %x, double %y) {
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%z = call double @llvm.maxnum.f64(double %x, double %y) readnone
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ret double %z
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}
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; CHECK-LABEL: @test_intrinsic_fmaxl
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; CHECK: callq fmaxl
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define x86_fp80 @test_intrinsic_fmaxl(x86_fp80 %x, x86_fp80 %y) {
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%z = call x86_fp80 @llvm.maxnum.f80(x86_fp80 %x, x86_fp80 %y) readnone
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ret x86_fp80 %z
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}
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; CHECK-LABEL: @test_intrinsic_fmax_v2f32
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; SSE: movaps %xmm1, %xmm2
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; SSE-NEXT: maxps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vmaxps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define <2 x float> @test_intrinsic_fmax_v2f32(<2 x float> %x, <2 x float> %y) {
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%z = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %x, <2 x float> %y) readnone
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ret <2 x float> %z
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}
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; CHECK-LABEL: @test_intrinsic_fmax_v4f32
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; SSE: movaps %xmm1, %xmm2
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; SSE-NEXT: maxps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vmaxps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define <4 x float> @test_intrinsic_fmax_v4f32(<4 x float> %x, <4 x float> %y) {
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%z = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float> %y) readnone
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ret <4 x float> %z
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}
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; CHECK-LABEL: @test_intrinsic_fmax_v2f64
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; SSE: movapd %xmm1, %xmm2
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; SSE-NEXT: maxpd %xmm0, %xmm2
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vmaxpd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define <2 x double> @test_intrinsic_fmax_v2f64(<2 x double> %x, <2 x double> %y) {
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%z = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %x, <2 x double> %y) readnone
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ret <2 x double> %z
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}
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; CHECK-LABEL: @test_intrinsic_fmax_v4f64
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; SSE: movapd %xmm2, %xmm4
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; SSE-NEXT: maxpd %xmm0, %xmm4
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm2
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; SSE-NEXT: andnpd %xmm4, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: movapd %xmm3, %xmm2
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; SSE-NEXT: maxpd %xmm1, %xmm2
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; SSE-NEXT: cmpunordpd %xmm1, %xmm1
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: andnpd %xmm2, %xmm1
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; SSE-NEXT: orpd %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX: vmaxpd %ymm0, %ymm1, %ymm2
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; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0
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; AVX-NEXT: retq
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define <4 x double> @test_intrinsic_fmax_v4f64(<4 x double> %x, <4 x double> %y) {
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%z = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %x, <4 x double> %y) readnone
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ret <4 x double> %z
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}
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; CHECK-LABEL: @test_intrinsic_fmax_v8f64
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; SSE: movapd %xmm4, %xmm8
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; SSE-NEXT: maxpd %xmm0, %xmm8
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm4
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; SSE-NEXT: andnpd %xmm8, %xmm0
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; SSE-NEXT: orpd %xmm4, %xmm0
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; SSE-NEXT: movapd %xmm5, %xmm4
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; SSE-NEXT: maxpd %xmm1, %xmm4
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; SSE-NEXT: cmpunordpd %xmm1, %xmm1
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; SSE-NEXT: andpd %xmm1, %xmm5
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; SSE-NEXT: andnpd %xmm4, %xmm1
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; SSE-NEXT: orpd %xmm5, %xmm1
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; SSE-NEXT: movapd %xmm6, %xmm4
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; SSE-NEXT: maxpd %xmm2, %xmm4
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; SSE-NEXT: cmpunordpd %xmm2, %xmm2
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; SSE-NEXT: andpd %xmm2, %xmm6
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; SSE-NEXT: andnpd %xmm4, %xmm2
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; SSE-NEXT: orpd %xmm6, %xmm2
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; SSE-NEXT: movapd %xmm7, %xmm4
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; SSE-NEXT: maxpd %xmm3, %xmm4
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; SSE-NEXT: cmpunordpd %xmm3, %xmm3
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; SSE-NEXT: andpd %xmm3, %xmm7
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; SSE-NEXT: andnpd %xmm4, %xmm3
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; SSE-NEXT: orpd %xmm7, %xmm3
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; SSE-NEXT: retq
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;
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; AVX: vmaxpd %ymm0, %ymm2, %ymm4
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; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vblendvpd %ymm0, %ymm2, %ymm4, %ymm0
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; AVX-NEXT: vmaxpd %ymm1, %ymm3, %ymm2
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; AVX-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm1
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; AVX-NEXT: vblendvpd %ymm1, %ymm3, %ymm2, %ymm1
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; AVX-NEXT: retq
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define <8 x double> @test_intrinsic_fmax_v8f64(<8 x double> %x, <8 x double> %y) {
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%z = call <8 x double> @llvm.maxnum.v8f64(<8 x double> %x, <8 x double> %y) readnone
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ret <8 x double> %z
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}
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