74a1eef7c4
Try to reverse the constant-shrinking that happens in SimplifyDemandedBits() for 'and' masks when it results in a smaller sign-extended immediate. We are also able to detect dead 'and' ops here (the mask is all ones). In that case, we replace and return without selecting the 'and'. Other targets might want to share some of this logic by enabling this under a target hook, but I didn't see diffs for simple cases with PowerPC or AArch64, so they may already have some specialized logic for this kind of thing or have different needs. This should solve PR35907: https://bugs.llvm.org/show_bug.cgi?id=35907 Differential Revision: https://reviews.llvm.org/D42088 llvm-svn: 322957
15 lines
384 B
LLVM
15 lines
384 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
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define i64 @test(i64 %A) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0:
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; CHECK-NEXT: shrq $54, %rdi
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; CHECK-NEXT: andq $-4, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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%B = lshr i64 %A, 56
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%C = shl i64 %B, 2
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ret i64 %C
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}
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