0a0cac6dbd
Change definition of expandBitCastI128ToF128 and expandBitCastF128ToI128 to allow for simplified use in atomic load/store. Update logic to split 128-bit loads and stores in DAGCombine to also handle the f128 case where appropriate. This fixes the regressions introduced by recent atomic load/store patches.
102 lines
2.9 KiB
LLVM
102 lines
2.9 KiB
LLVM
; Test long double atomic stores - via i128.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefixes=CHECK,BASE %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck -check-prefixes=CHECK,Z13 %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mattr=+soft-float | FileCheck -check-prefixes=SOFTFP %s
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define void @f1(ptr %dst, ptr %src) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lg %r1, 8(%r3)
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; CHECK-NEXT: lg %r0, 0(%r3)
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; CHECK-NEXT: stpq %r0, 0(%r2)
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; CHECK-NEXT: bcr 1{{[45]}}, %r0
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; CHECK-NEXT: br %r14
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; SOFTFP-LABEL: f1:
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; SOFTFP: # %bb.0:
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; SOFTFP-NEXT: lg %r1, 8(%r3)
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; SOFTFP-NEXT: lg %r0, 0(%r3)
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; SOFTFP-NEXT: stpq %r0, 0(%r2)
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; SOFTFP-NEXT: bcr 1{{[45]}}, %r0
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; SOFTFP-NEXT: br %r14
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%val = load fp128, ptr %src, align 8
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store atomic fp128 %val, ptr %dst seq_cst, align 16
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ret void
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}
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define void @f1_fpsrc(ptr %dst, ptr %src) {
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; CHECK-LABEL: f1_fpsrc:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ld %f0, 0(%r3)
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; CHECK-NEXT: ld %f2, 8(%r3)
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; CHECK-NEXT: axbr %f0, %f0
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; BASE-NEXT: lgdr %r1, %f2
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; BASE-NEXT: lgdr %r0, %f0
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; Z13-NEXT: vmrhg %v0, %v0, %v2
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; Z13-NEXT: vlgvg %r1, %v0, 1
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; Z13-NEXT: vlgvg %r0, %v0, 0
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; CHECK-NEXT: stpq %r0, 0(%r2)
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; CHECK-NEXT: bcr 1{{[45]}}, %r0
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; CHECK-NEXT: br %r14
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; SOFTFP-LABEL: f1_fpsrc:
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; SOFTFP: lg %r0, 8(%r3)
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; SOFTFP-NEXT: lg %r1, 0(%r3)
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; SOFTFP-NEXT: lgr %r13, %r2
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; SOFTFP-NEXT: stg %r0, 168(%r15)
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; SOFTFP-NEXT: stg %r1, 160(%r15)
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; SOFTFP-NEXT: stg %r0, 184(%r15)
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; SOFTFP-NEXT: la %r2, 192(%r15)
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; SOFTFP-NEXT: la %r3, 176(%r15)
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; SOFTFP-NEXT: la %r4, 160(%r15)
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; SOFTFP-NEXT: stg %r1, 176(%r15)
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; SOFTFP-NEXT: brasl %r14, __addtf3@PLT
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; SOFTFP-NEXT: lg %r1, 200(%r15)
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; SOFTFP-NEXT: lg %r0, 192(%r15)
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; SOFTFP-NEXT: stpq %r0, 0(%r13)
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; SOFTFP-NEXT: bcr 1{{[45]}}, %r0
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; SOFTFP-NEXT: lmg %r13, %r15, 312(%r15)
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; SOFTFP-NEXT: br %r14
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%val = load fp128, ptr %src, align 8
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%add = fadd fp128 %val, %val
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store atomic fp128 %add, ptr %dst seq_cst, align 16
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ret void
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}
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define void @f2(ptr %dst, ptr %src) {
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; CHECK-LABEL: f2:
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; CHECK: brasl %r14, __atomic_store@PLT
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%val = load fp128, ptr %src, align 8
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store atomic fp128 %val, ptr %dst seq_cst, align 8
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ret void
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}
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define void @f2_fpuse(ptr %dst, ptr %src) {
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; CHECK-LABEL: f2_fpuse:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -176
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; CHECK-NEXT: .cfi_def_cfa_offset 336
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; CHECK-NEXT: ld %f0, 0(%r3)
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; CHECK-NEXT: ld %f2, 8(%r3)
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; CHECK-DAG: lgr %r3, %r2
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; CHECK-DAG: axbr %f0, %f0
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; CHECK-NEXT: la %r4, 160(%r15)
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; CHECK-NEXT: lghi %r2, 16
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; CHECK-NEXT: lhi %r5, 5
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; CHECK-NEXT: std %f0, 160(%r15)
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; CHECK-NEXT: std %f2, 168(%r15)
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; CHECK-NEXT: brasl %r14, __atomic_store@PLT
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%val = load fp128, ptr %src, align 8
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%add = fadd fp128 %val, %val
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store atomic fp128 %add, ptr %dst seq_cst, align 8
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ret void
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}
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