189900eb14
This stops reporting CostPerUse 1 for `R8`-`R15` and `XMM8`-`XMM31`.
This was previously done because instruction encoding require a REX
prefix when using them resulting in longer instruction encodings. I
found that this regresses the quality of the register allocation as the
costs impose an ordering on eviction candidates. I also feel that there
is a bit of an impedance mismatch as the actual costs occure when
encoding instructions using those registers, but the order of VReg
assignments is not primarily ordered by number of Defs+Uses.
I did extensive measurements with the llvm-test-suite wiht SPEC2006 +
SPEC2017 included, internal services showed similar patterns. Generally
there are a log of improvements but also a lot of regression. But on
average the allocation quality seems to improve at a small code size
regression.
Results for measuring static and dynamic instruction counts:
Dynamic Counts (scaled by execution frequency) / Optimization Remarks:
Spills+FoldedSpills -5.6%
Reloads+FoldedReloads -4.2%
Copies -0.1%
Static / LLVM Statistics:
regalloc.NumSpills mean -1.6%, geomean -2.8%
regalloc.NumReloads mean -1.7%, geomean -3.1%
size..text mean +0.4%, geomean +0.4%
Static / LLVM Statistics:
mean -2.2%, geomean -3.1%) regalloc.NumSpills
mean -2.6%, geomean -3.9%) regalloc.NumReloads
mean +0.6%, geomean +0.6%) size..text
Static / LLVM Statistics:
regalloc.NumSpills mean -3.0%
regalloc.NumReloads mean -3.3%
size..text mean +0.3%, geomean +0.3%
Differential Revision: https://reviews.llvm.org/D133902
29 lines
1.3 KiB
LLVM
29 lines
1.3 KiB
LLVM
; RUN: llc < %s -tailcallopt -mcpu=generic -mtriple=x86_64-linux -post-RA-scheduler=true | FileCheck %s
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; RUN: llc < %s -tailcallopt -mcpu=generic -mtriple=x86_64-win32 -post-RA-scheduler=true | FileCheck %s
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; FIXME: Redundant unused stack allocation could be eliminated.
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; CHECK: subq ${{24|72|80}}, %rsp
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; Check that lowered arguments on the stack do not overwrite each other.
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; Add %in1 %p1 to a different temporary register (%eax).
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; CHECK: movl [[A1:32|144]](%rsp), [[R1:%e..|%r.*d]]
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; Move param %in1 to temp register (%r10d).
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; CHECK: movl [[A2:40|152]](%rsp), [[R2:%[a-z0-9]+]]
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; Add %in1 %p1 to a different temporary register (%eax).
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; CHECK: addl {{%edi|%ecx}}, [[R1]]
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; Move param %in2 to stack.
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; CHECK-DAG: movl [[R2]], [[A1]](%rsp)
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; Move result of addition to stack.
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; CHECK-DAG: movl [[R1]], [[A2]](%rsp)
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; Eventually, do a TAILCALL
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; CHECK: TAILCALL
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declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b) nounwind
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define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) nounwind {
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entry:
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%tmp = add i32 %in1, %p1
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%retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp)
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ret i32 %retval
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}
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