fb86b3d96b
Need to set the insertion point for (non-schedulable) vector node after
the last instruction in the node to avoid def-use breakage. But it also
causes miscompilation with gather/buildvector operands of the phi nodes,
used in the same phi only in the block.
These nodes supposed to be inserted at the end of the block and after
changing the insertion point for the non-schedulable vec block, it also
may break def-use dependencies. Need to prevector such nodes, to emit
them as early as possible, so the vectorized nodes are inserted before
these nodes.
Fixes #139728
Recommit after revert 60fb921792
Reviewers: hiraditya, HanKuanChen, RKSimon
Reviewed By: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/139917
60 lines
2.3 KiB
LLVM
60 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=haswell < %s | FileCheck %s
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define void @test(float %0) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[TMP0]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> <float 0.000000e+00, float poison>, <2 x i32> <i32 2, i32 0>
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; CHECK-NEXT: [[TMP5:%.*]] = fdiv <2 x float> [[TMP4]], zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = fdiv <2 x float> [[TMP6]], zeroinitializer
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; CHECK-NEXT: br label %[[BB6:.*]]
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; CHECK: [[BB6]]:
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; CHECK-NEXT: [[TMP7:%.*]] = fmul <2 x float> [[TMP5]], zeroinitializer
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; CHECK-NEXT: [[TMP8:%.*]] = fsub <2 x float> zeroinitializer, [[TMP7]]
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; CHECK-NEXT: br label %[[BB10:.*]]
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; CHECK: [[BB9:.*]]:
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; CHECK-NEXT: br label %[[BB10]]
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; CHECK: [[BB10]]:
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; CHECK-NEXT: [[TMP11:%.*]] = phi <2 x float> [ [[TMP8]], %[[BB6]] ], [ poison, %[[BB9]] ]
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; CHECK-NEXT: br label %[[BB12:.*]]
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; CHECK: [[BB12]]:
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; CHECK-NEXT: [[TMP13:%.*]] = fmul <2 x float> [[TMP3]], zeroinitializer
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; CHECK-NEXT: [[TMP14:%.*]] = fsub <2 x float> [[TMP11]], [[TMP13]]
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; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x float> [[TMP14]], i32 0
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; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x float> [[TMP14]], i32 1
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; CHECK-NEXT: [[TMP17:%.*]] = fadd float [[TMP15]], [[TMP16]]
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; CHECK-NEXT: [[TMP18:%.*]] = call float @llvm.fabs.f32(float [[TMP17]])
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; CHECK-NEXT: ret void
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;
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%2 = fdiv float 0.000000e+00, 0.000000e+00
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%3 = fdiv float 0.000000e+00, 0.000000e+00
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%4 = fdiv float %0, 0.000000e+00
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br label %5
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5:
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%6 = fmul float %4, 0.000000e+00
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%7 = fsub float 0.000000e+00, %6
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%8 = fmul float %3, 0.000000e+00
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%9 = fsub float 0.000000e+00, %8
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br label %11
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10:
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br label %11
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11:
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%12 = phi float [ %7, %5 ], [ 0.000000e+00, %10 ]
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%13 = phi float [ %9, %5 ], [ 0.000000e+00, %10 ]
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br label %14
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14:
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%15 = fmul float %2, 0.000000e+00
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%16 = fsub float %12, %15
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%17 = fmul float %4, 0.000000e+00
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%18 = fsub float %13, %17
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%19 = fadd float %16, %18
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%20 = call float @llvm.fabs.f32(float %19)
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ret void
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}
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