766cb615a3
I never completed the work on the patches referenced by
f8bf7d7f42, but this was intended to
avoid folding immediate writes into m0 which the coalescer doesn't
understand very well. Relax this to allow simple SGPR immediates to
fold directly into VGPR copies. This pattern shows up routinely in
current GlobalISel code since nothing is smart enough to emit VGPR
constants yet.
132 lines
5.7 KiB
LLVM
132 lines
5.7 KiB
LLVM
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-unknown -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s
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; ALL-LABEL: {{^}}test:
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; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 8
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; HSA: kernarg_segment_alignment = 4
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; CO-V2: s_load_dword s{{[0-9]+}}, s[4:5], 0xa
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; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0xa
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define amdgpu_kernel void @test(i32 addrspace(1)* %out) #1 {
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%kernarg.segment.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%header.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
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%gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
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%value = load i32, i32 addrspace(4)* %gep
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; ALL-LABEL: {{^}}test_implicit:
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; HSA: kernarg_segment_byte_size = 8
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; OS-MESA3D: kernarg_segment_byte_size = 24
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; CO-V2: kernarg_segment_alignment = 4
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; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15
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; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x15
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define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 {
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%implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%header.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
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%value = load i32, i32 addrspace(4)* %gep
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; ALL-LABEL: {{^}}test_implicit_alignment:
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; HSA: kernarg_segment_byte_size = 12
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; OS-MESA3D: kernarg_segment_byte_size = 28
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; CO-V2: kernarg_segment_alignment = 4
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; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
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; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
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; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
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; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
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; ALL: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
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define amdgpu_kernel void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #1 {
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%implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%val = load i32, i32 addrspace(4)* %arg.ptr
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; ALL-LABEL: {{^}}opencl_test_implicit_alignment
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; HSA: kernarg_segment_byte_size = 64
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; OS-MESA3D: kernarg_segment_byte_size = 28
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; CO-V2: kernarg_segment_alignment = 4
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; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
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; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
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; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
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; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
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; ALL: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
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define amdgpu_kernel void @opencl_test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #2 {
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%implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%val = load i32, i32 addrspace(4)* %arg.ptr
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; ALL-LABEL: {{^}}test_no_kernargs:
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; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 0
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; OS-MESA3D: kernarg_segment_byte_size = 16
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; CO-V2: kernarg_segment_alignment = 4
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; HSA: s_load_dword s{{[0-9]+}}, s[4:5]
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define amdgpu_kernel void @test_no_kernargs() #1 {
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%kernarg.segment.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%header.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
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%gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
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%value = load i32, i32 addrspace(4)* %gep
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store volatile i32 %value, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs:
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; HSA: kernarg_segment_byte_size = 48
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; OS-MESA3d: kernarg_segment_byte_size = 16
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; CO-V2: kernarg_segment_alignment = 4
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define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs() #2 {
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%implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%val = load volatile i32, i32 addrspace(4)* %arg.ptr
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store volatile i32 %val, i32 addrspace(1)* null
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ret void
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}
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; GCN-LABEL: {{^}}opencl_test_implicit_alignment_no_explicit_kernargs_round_up:
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; HSA: kernarg_segment_byte_size = 40
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; OS-MESA3D: kernarg_segment_byte_size = 16
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; CO-V2: kernarg_segment_alignment = 4
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define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs_round_up() #3 {
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%implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%val = load volatile i32, i32 addrspace(4)* %arg.ptr
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store volatile i32 %val, i32 addrspace(1)* null
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ret void
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}
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; ALL-LABEL: {{^}}func_kernarg_segment_ptr:
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; ALL: v_mov_b32_e32 v0, 0{{$}}
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; ALL: v_mov_b32_e32 v1, 0{{$}}
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define i8 addrspace(4)* @func_kernarg_segment_ptr() {
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%ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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ret i8 addrspace(4)* %ptr
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}
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declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
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declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="48" }
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attributes #3 = { nounwind "amdgpu-implicitarg-num-bytes"="38" }
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