79f67cae91
The hardware has created a real mess in the naming for add/sub, which have been renamed basically every generation. Switch the carry out pseudos to have the gfx9/gfx10 names. We were using the original SI/CI v_add_i32/v_sub_i32 names. Later targets reintroduced these names as carryless instructions with a saturating clamp bit, which we do not define. Do this rename so we can unambiguously add these missing instructions. The carry-in versions should also be renamed, but at least those had a consistent _u32 name to begin with. The 16-bit instructions were also renamed, but aren't ambiguous. This does regress assembler error message quality in some cases. In mismatched wave32/wave64 situations, this will switch from "unsupported instruction" to "invalid operand", with the error pointing at the wrong position. I couldn't quite follow how the assembler selects these, but the previous behavior seemed accidental to me. It looked like there was a partial attempt to handle this which was never completed (i.e. there is an AMDGPUOperand::isBoolReg but it isn't used for anything).
89 lines
3.5 KiB
YAML
89 lines
3.5 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=kaveri -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=CI -check-prefix=GCN %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
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# GCN-LABEL: {{^}}name: add_shr_i32
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# GCN: [[SMOV:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 123
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# CI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec
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# CI: %{{[0-9]+}}:vgpr_32 = V_ADD_CO_U32_e32 [[SMOV]], killed [[SHIFT]], implicit-def $vcc, implicit $exec
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# VI: [[VMOV:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 [[SMOV]], implicit $exec
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# VI: %{{[0-9]+}}:vgpr_32 = V_ADD_CO_U32_sdwa 0, [[VMOV]], 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit-def $vcc, implicit $exec
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# GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_CO_U32_sdwa 0, [[SMOV]], 0, %{{[0-9]+}}, 0, 6, 0, 6, 5, implicit-def $vcc, implicit $exec
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---
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name: add_shr_i32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_64 }
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- { id: 1, class: vreg_64 }
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- { id: 2, class: sreg_64 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_32_xm0 }
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- { id: 5, class: sreg_32_xm0 }
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- { id: 6, class: sreg_32 }
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- { id: 7, class: sreg_32_xm0 }
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- { id: 8, class: sreg_32 }
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- { id: 9, class: vgpr_32 }
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- { id: 10, class: vgpr_32 }
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- { id: 11, class: vgpr_32 }
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- { id: 12, class: sreg_32_xm0 }
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
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%2 = COPY $sgpr30_sgpr31
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%1 = COPY $vgpr2_vgpr3
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%0 = COPY $vgpr0_vgpr1
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%3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
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%12 = S_MOV_B32 123
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%10 = V_LSHRREV_B32_e64 16, %3, implicit $exec
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%11 = V_ADD_CO_U32_e32 %12, killed %10, implicit-def $vcc, implicit $exec
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FLAT_STORE_DWORD %0, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
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$sgpr30_sgpr31 = COPY %2
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S_SETPC_B64_return $sgpr30_sgpr31
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...
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# GCN-LABEL: {{^}}name: trunc_shr_f32
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# CI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec
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# CI: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit $mode, implicit $exec, implicit-def $vcc
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# VI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec
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# VI: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit $mode, implicit $exec, implicit-def $vcc
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# GFX9: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_sdwa 0, %{{[0-9]+}}, 1, 2, 6, 0, 5, implicit $mode, implicit $exec
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---
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name: trunc_shr_f32
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_64 }
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- { id: 1, class: vreg_64 }
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- { id: 2, class: sreg_64 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_32_xm0 }
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- { id: 5, class: sreg_32_xm0 }
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- { id: 6, class: sreg_32 }
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- { id: 7, class: sreg_32_xm0 }
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- { id: 8, class: sreg_32 }
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- { id: 9, class: vgpr_32 }
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- { id: 10, class: vgpr_32 }
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- { id: 11, class: vgpr_32 }
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
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%2 = COPY $sgpr30_sgpr31
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%1 = COPY $vgpr2_vgpr3
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%0 = COPY $vgpr0_vgpr1
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%3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
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%10 = V_LSHRREV_B32_e64 16, %3, implicit $exec
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%11 = V_TRUNC_F32_e64 0, killed %10, 1, 2, implicit $mode, implicit $exec, implicit-def $vcc
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FLAT_STORE_DWORD %0, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
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$sgpr30_sgpr31 = COPY %2
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S_SETPC_B64_return $sgpr30_sgpr31
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