6f6d389da5
When splitting a live interval with subranges, only insert copies for
the lanes that are live at the point of the split. This avoids some
unnecessary copies and fixes a problem where copying dead lanes was
generating MIR that failed verification. The test case for this is
test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir.
Without this fix, some earlier live range splitting would create %430:
%430 [256r,848r:0)[848r,2584r:1) 0@256r 1@848r L0000000000000003 [848r,2584r:0) 0@848r L0000000000000030 [256r,2584r:0) 0@256r weight:1.480938e-03
...
256B undef %430.sub2:vreg_128 = V_LSHRREV_B32_e32 16, %20.sub1:vreg_128, implicit $exec
...
848B %430.sub0:vreg_128 = V_AND_B32_e32 %92:sreg_32, %20.sub1:vreg_128, implicit $exec
...
2584B %431:vreg_128 = COPY %430:vreg_128
Then RAGreedy::tryLocalSplit would split %430 into %432 and %433 just
before 848B giving:
%432 [256r,844r:0) 0@256r L0000000000000030 [256r,844r:0) 0@256r weight:3.066802e-03
%433 [844r,848r:0)[848r,2584r:1) 0@844r 1@848r L0000000000000030 [844r,2584r:0) 0@844r L0000000000000003 [844r,844d:0)[848r,2584r:1) 0@844r 1@848r weight:2.831776e-03
...
256B undef %432.sub2:vreg_128 = V_LSHRREV_B32_e32 16, %20.sub1:vreg_128, implicit $exec
...
844B undef %433.sub0:vreg_128 = COPY %432.sub0:vreg_128 {
internal %433.sub2:vreg_128 = COPY %432.sub2:vreg_128
848B }
%433.sub0:vreg_128 = V_AND_B32_e32 %92:sreg_32, %20.sub1:vreg_128, implicit $exec
...
2584B %431:vreg_128 = COPY %433:vreg_128
Note that the copy from %432 to %433 at 844B is a curious
bundle-without-a-BUNDLE-instruction that SplitKit creates deliberately,
and it includes a copy of .sub0 which is not live at this point, and
that causes it to fail verification:
*** Bad machine code: No live subrange at use ***
- function: zextload_global_v64i16_to_v64i64
- basic block: %bb.0 (0x7faed48) [0B;2848B)
- instruction: 844B undef %433.sub0:vreg_128 = COPY %432.sub0:vreg_128
- operand 1: %432.sub0:vreg_128
- interval: %432 [256r,844r:0) 0@256r L0000000000000030 [256r,844r:0) 0@256r weight:3.066802e-03
- at: 844B
Using real bundles with a BUNDLE instruction might also fix this
problem, but the current fix is less invasive and also avoids some
unnecessary copies.
https://bugs.llvm.org/show_bug.cgi?id=47492
Differential Revision: https://reviews.llvm.org/D87757
99 lines
4.7 KiB
LLVM
99 lines
4.7 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck -check-prefixes=CHECK,GFX6 %s
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; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck -check-prefixes=CHECK,GFX7 %s
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;
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; There is something about Tonga that causes this test to spend a lot of time
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; in the default register allocator.
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; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
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; is used to calculate the scratch load/store address. Make sure that this
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; mechanism works even when many spills happen.
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; Just test that it compiles successfully.
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; CHECK-LABEL: test
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define amdgpu_kernel void @test(<1280 x i32> addrspace(1)* %out, <1280 x i32> addrspace(1)* %in) {
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entry:
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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%aptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %in, i32 %tid
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%a = load <1280 x i32>, <1280 x i32> addrspace(1)* %aptr
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; mark most VGPR registers as used to increase register pressure
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call void asm sideeffect "", "~{v4},~{v8},~{v12},~{v16},~{v20},~{v24},~{v28},~{v32}" ()
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call void asm sideeffect "", "~{v36},~{v40},~{v44},~{v48},~{v52},~{v56},~{v60},~{v64}" ()
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call void asm sideeffect "", "~{v68},~{v72},~{v76},~{v80},~{v84},~{v88},~{v92},~{v96}" ()
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call void asm sideeffect "", "~{v100},~{v104},~{v108},~{v112},~{v116},~{v120},~{v124},~{v128}" ()
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call void asm sideeffect "", "~{v132},~{v136},~{v140},~{v144},~{v148},~{v152},~{v156},~{v160}" ()
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call void asm sideeffect "", "~{v164},~{v168},~{v172},~{v176},~{v180},~{v184},~{v188},~{v192}" ()
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call void asm sideeffect "", "~{v196},~{v200},~{v204},~{v208},~{v212},~{v216},~{v220},~{v224}" ()
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%outptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %out, i32 %tid
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store <1280 x i32> %a, <1280 x i32> addrspace(1)* %outptr
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ret void
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}
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; CHECK-LABEL: test_limited_sgpr
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; GFX6: s_add_u32 s32, s32, 0x[[OFFSET:[0-9]+]]
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; GFX6-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[{{[0-9:]+}}], s32
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; GFX6-NEXT: s_sub_u32 s32, s32, 0x[[OFFSET:[0-9]+]]
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; GFX6: NumSgprs: 48
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; GFX6: ScratchSize: 8608
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define amdgpu_kernel void @test_limited_sgpr(<64 x i32> addrspace(1)* %out, <64 x i32> addrspace(1)* %in) #0 {
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entry:
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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; allocate enough scratch to go beyond 2^12 addressing
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%scratch = alloca <1280 x i32>, align 8, addrspace(5)
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; load VGPR data
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%aptr = getelementptr <64 x i32>, <64 x i32> addrspace(1)* %in, i32 %tid
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%a = load <64 x i32>, <64 x i32> addrspace(1)* %aptr
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; make sure scratch is used
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%x = extractelement <64 x i32> %a, i32 0
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%sptr0 = getelementptr <1280 x i32>, <1280 x i32> addrspace(5)* %scratch, i32 %x, i32 0
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store i32 1, i32 addrspace(5)* %sptr0
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; fill up SGPRs
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%sgpr0 = call <8 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr1 = call <8 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr2 = call <8 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr3 = call <8 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr4 = call <4 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr5 = call <2 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr6 = call <2 x i32> asm sideeffect "; def $0", "=s" ()
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%sgpr7 = call i32 asm sideeffect "; def $0", "=s" ()
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%cmp = icmp eq i32 %x, 0
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br i1 %cmp, label %bb0, label %ret
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bb0:
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; create SGPR pressure
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call void asm sideeffect "; use $0,$1,$2,$3,$4,$5,$6", "s,s,s,s,s,s,s,s"(<8 x i32> %sgpr0, <8 x i32> %sgpr1, <8 x i32> %sgpr2, <8 x i32> %sgpr3, <4 x i32> %sgpr4, <2 x i32> %sgpr5, <2 x i32> %sgpr6, i32 %sgpr7)
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; mark most VGPR registers as used to increase register pressure
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call void asm sideeffect "", "~{v4},~{v8},~{v12},~{v16},~{v20},~{v24},~{v28},~{v32}" ()
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call void asm sideeffect "", "~{v36},~{v40},~{v44},~{v48},~{v52},~{v56},~{v60},~{v64}" ()
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call void asm sideeffect "", "~{v68},~{v72},~{v76},~{v80},~{v84},~{v88},~{v92},~{v96}" ()
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call void asm sideeffect "", "~{v100},~{v104},~{v108},~{v112},~{v116},~{v120},~{v124},~{v128}" ()
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call void asm sideeffect "", "~{v132},~{v136},~{v140},~{v144},~{v148},~{v152},~{v156},~{v160}" ()
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call void asm sideeffect "", "~{v164},~{v168},~{v172},~{v176},~{v180},~{v184},~{v188},~{v192}" ()
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call void asm sideeffect "", "~{v196},~{v200},~{v204},~{v208},~{v212},~{v216},~{v220},~{v224}" ()
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br label %ret
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ret:
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%outptr = getelementptr <64 x i32>, <64 x i32> addrspace(1)* %out, i32 %tid
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store <64 x i32> %a, <64 x i32> addrspace(1)* %outptr
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ret void
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}
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
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declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
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attributes #0 = { "amdgpu-waves-per-eu"="10,10" }
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attributes #1 = { nounwind readnone }
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