7fff1fbd3c
This hashing scheme has been useful out of tree, and I want to start experimenting with it. Specifically I want to experiment on the MIRVRegNamer, MIRCanononicalizer, and eventually the MachineOutliner. This diff is a first step, that optionally brings stable hashing to the MIRVRegNamer (and as a result, the MIRCanonicalizer). We've tested this hashing scheme on a lot of MachineOperand types that llvm::hash_value can not handle in a stable manner. This stable hashing was also the basis for "Global Machine Outliner for ThinLTO" in EuroLLVM 2020 http://llvm.org/devmtg/2020-04/talks.html#TechTalk_58 Credits: Kyungwoo Lee, Nikolai Tillmann Differential Revision: https://reviews.llvm.org/D86952
30 lines
1.3 KiB
YAML
30 lines
1.3 KiB
YAML
# RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=amdgcn -run-pass mir-canonicalizer -verify-machineinstrs -o - %s
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# RUN: llc -march=amdgcn -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s
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# Previously getReservedRegs was called before parsing
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# machineFunctionInfo, but the AMDGPU implementation depends on
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# setting register fields to reserve there. $sgpr50 would then not be
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# reserved, resulting in a verifier error from an undefined register.
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---
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# CHECK: machineFunctionInfo:
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# CHECK: isEntryFunction: true
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# CHECK: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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# CHECK: frameOffsetReg: '$sgpr50'
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# CHECK: renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50, 4, 0, 0, 0, 0, 0, implicit $exec :: (load 4, addrspace 5)
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name: reserve_correct_register
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr50'
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stack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
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body: |
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bb.0:
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renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50, 4, 0, 0, 0, 0, 0, implicit $exec :: (load 4, addrspace 5)
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S_ENDPGM 0
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...
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