969e703427
Summary: RISC-V uses a post-select peephole pass to optimise `(load/store (ADDI $reg, %lo(addr)), 0)` into `(load/store $reg, %lo(addr))`. This peephole wasn't firing for accesses to constant pools, which is how we materialise most floating point constants. This adds support for the constantpool case, which improves code generation for lots of small FP loading examples. I have not added any tests because this structure is well-covered by the `fp-imm.ll` testcases, as well as almost all other uses of floating point constants in the RISC-V backend tests. Reviewed By: luismarques, asb Differential Revision: https://reviews.llvm.org/D79523
268 lines
11 KiB
LLVM
268 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+d \
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; RUN: -target-abi ilp32d < %s \
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; RUN: | FileCheck -check-prefix=RV32-ILP32D %s
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; This file contains tests that will have differing output for the ilp32 and
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; ilp32f ABIs.
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define i32 @callee_double_in_fpr(i32 %a, double %b) nounwind {
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; RV32-ILP32D-LABEL: callee_double_in_fpr:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: fcvt.w.d a1, fa0, rtz
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; RV32-ILP32D-NEXT: add a0, a0, a1
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; RV32-ILP32D-NEXT: ret
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%b_fptosi = fptosi double %b to i32
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%1 = add i32 %a, %b_fptosi
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ret i32 %1
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}
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define i32 @caller_double_in_fpr() nounwind {
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; RV32-ILP32D-LABEL: caller_double_in_fpr:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: addi sp, sp, -16
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; RV32-ILP32D-NEXT: sw ra, 12(sp)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI1_0)
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; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI1_0)(a0)
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; RV32-ILP32D-NEXT: addi a0, zero, 1
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; RV32-ILP32D-NEXT: call callee_double_in_fpr
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; RV32-ILP32D-NEXT: lw ra, 12(sp)
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; RV32-ILP32D-NEXT: addi sp, sp, 16
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; RV32-ILP32D-NEXT: ret
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%1 = call i32 @callee_double_in_fpr(i32 1, double 2.0)
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ret i32 %1
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}
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; Must keep define on a single line due to an update_llc_test_checks.py limitation
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define i32 @callee_double_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, double %f) nounwind {
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; RV32-ILP32D-LABEL: callee_double_in_fpr_exhausted_gprs:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: lw a0, 0(sp)
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; RV32-ILP32D-NEXT: fcvt.w.d a1, fa0, rtz
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; RV32-ILP32D-NEXT: add a0, a0, a1
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; RV32-ILP32D-NEXT: ret
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%f_fptosi = fptosi double %f to i32
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%1 = add i32 %e, %f_fptosi
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ret i32 %1
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}
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define i32 @caller_double_in_fpr_exhausted_gprs() nounwind {
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; RV32-ILP32D-LABEL: caller_double_in_fpr_exhausted_gprs:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: addi sp, sp, -16
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; RV32-ILP32D-NEXT: sw ra, 12(sp)
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; RV32-ILP32D-NEXT: addi a1, zero, 5
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI3_0)
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; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI3_0)(a0)
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; RV32-ILP32D-NEXT: addi a0, zero, 1
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; RV32-ILP32D-NEXT: addi a2, zero, 2
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; RV32-ILP32D-NEXT: addi a4, zero, 3
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; RV32-ILP32D-NEXT: addi a6, zero, 4
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; RV32-ILP32D-NEXT: sw a1, 0(sp)
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; RV32-ILP32D-NEXT: mv a1, zero
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; RV32-ILP32D-NEXT: mv a3, zero
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; RV32-ILP32D-NEXT: mv a5, zero
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; RV32-ILP32D-NEXT: mv a7, zero
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; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs
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; RV32-ILP32D-NEXT: lw ra, 12(sp)
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; RV32-ILP32D-NEXT: addi sp, sp, 16
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; RV32-ILP32D-NEXT: ret
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%1 = call i32 @callee_double_in_fpr_exhausted_gprs(
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i64 1, i64 2, i64 3, i64 4, i32 5, double 6.0)
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ret i32 %1
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}
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; Must keep define on a single line due to an update_llc_test_checks.py limitation
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define i32 @callee_double_in_gpr_exhausted_fprs(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i) nounwind {
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; RV32-ILP32D-LABEL: callee_double_in_gpr_exhausted_fprs:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: addi sp, sp, -16
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; RV32-ILP32D-NEXT: sw a0, 8(sp)
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; RV32-ILP32D-NEXT: sw a1, 12(sp)
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; RV32-ILP32D-NEXT: fld ft0, 8(sp)
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; RV32-ILP32D-NEXT: fcvt.w.d a0, fa7, rtz
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; RV32-ILP32D-NEXT: fcvt.w.d a1, ft0, rtz
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; RV32-ILP32D-NEXT: add a0, a0, a1
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; RV32-ILP32D-NEXT: addi sp, sp, 16
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; RV32-ILP32D-NEXT: ret
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%h_fptosi = fptosi double %h to i32
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%i_fptosi = fptosi double %i to i32
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%1 = add i32 %h_fptosi, %i_fptosi
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ret i32 %1
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}
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define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
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; RV32-ILP32D-LABEL: caller_double_in_gpr_exhausted_fprs:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: addi sp, sp, -16
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; RV32-ILP32D-NEXT: sw ra, 12(sp)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_0)
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; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI5_0)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_1)
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; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI5_1)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_2)
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; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI5_2)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_3)
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; RV32-ILP32D-NEXT: fld fa3, %lo(.LCPI5_3)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_4)
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; RV32-ILP32D-NEXT: fld fa4, %lo(.LCPI5_4)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_5)
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; RV32-ILP32D-NEXT: fld fa5, %lo(.LCPI5_5)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_6)
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; RV32-ILP32D-NEXT: fld fa6, %lo(.LCPI5_6)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_7)
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; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI5_7)(a0)
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; RV32-ILP32D-NEXT: lui a1, 262688
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; RV32-ILP32D-NEXT: mv a0, zero
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; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs
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; RV32-ILP32D-NEXT: lw ra, 12(sp)
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; RV32-ILP32D-NEXT: addi sp, sp, 16
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; RV32-ILP32D-NEXT: ret
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%1 = call i32 @callee_double_in_gpr_exhausted_fprs(
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double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0,
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double 7.0, double 8.0, double 9.0)
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ret i32 %1
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}
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; Must keep define on a single line due to an update_llc_test_checks.py limitation
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define i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs(i64 %a, double %b, i64 %c, double %d, i64 %e, double %f, i32 %g, double %h, double %i, double %j, double %k, double %l, double %m) nounwind {
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; RV32-ILP32D-LABEL: callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: addi sp, sp, -16
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; RV32-ILP32D-NEXT: lw a0, 16(sp)
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; RV32-ILP32D-NEXT: sw a7, 8(sp)
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; RV32-ILP32D-NEXT: sw a0, 12(sp)
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; RV32-ILP32D-NEXT: fld ft0, 8(sp)
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; RV32-ILP32D-NEXT: fcvt.w.d a0, ft0, rtz
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; RV32-ILP32D-NEXT: add a0, a6, a0
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; RV32-ILP32D-NEXT: addi sp, sp, 16
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; RV32-ILP32D-NEXT: ret
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%m_fptosi = fptosi double %m to i32
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%1 = add i32 %g, %m_fptosi
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ret i32 %1
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}
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define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind {
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; RV32-ILP32D-LABEL: caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: addi sp, sp, -16
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; RV32-ILP32D-NEXT: sw ra, 12(sp)
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; RV32-ILP32D-NEXT: lui a1, 262816
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_0)
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; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI7_0)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_1)
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; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI7_1)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_2)
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; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI7_2)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_3)
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; RV32-ILP32D-NEXT: fld fa3, %lo(.LCPI7_3)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_4)
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; RV32-ILP32D-NEXT: fld fa4, %lo(.LCPI7_4)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_5)
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; RV32-ILP32D-NEXT: fld fa5, %lo(.LCPI7_5)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_6)
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; RV32-ILP32D-NEXT: fld fa6, %lo(.LCPI7_6)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_7)
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; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI7_7)(a0)
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; RV32-ILP32D-NEXT: addi a0, zero, 1
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; RV32-ILP32D-NEXT: addi a2, zero, 3
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; RV32-ILP32D-NEXT: addi a4, zero, 5
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; RV32-ILP32D-NEXT: addi a6, zero, 7
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; RV32-ILP32D-NEXT: sw a1, 0(sp)
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; RV32-ILP32D-NEXT: mv a1, zero
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; RV32-ILP32D-NEXT: mv a3, zero
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; RV32-ILP32D-NEXT: mv a5, zero
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; RV32-ILP32D-NEXT: mv a7, zero
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; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs
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; RV32-ILP32D-NEXT: lw ra, 12(sp)
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; RV32-ILP32D-NEXT: addi sp, sp, 16
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; RV32-ILP32D-NEXT: ret
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%1 = call i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs(
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i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i32 7, double 8.0,
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double 9.0, double 10.0, double 11.0, double 12.0, double 13.0)
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ret i32 %1
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}
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; Must keep define on a single line due to an update_llc_test_checks.py limitation
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define i32 @callee_double_on_stack_exhausted_gprs_fprs(i64 %a, double %b, i64 %c, double %d, i64 %e, double %f, i64 %g, double %h, double %i, double %j, double %k, double %l, double %m) nounwind {
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; RV32-ILP32D-LABEL: callee_double_on_stack_exhausted_gprs_fprs:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: fld ft0, 0(sp)
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; RV32-ILP32D-NEXT: fcvt.w.d a0, ft0, rtz
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; RV32-ILP32D-NEXT: add a0, a6, a0
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; RV32-ILP32D-NEXT: ret
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%g_trunc = trunc i64 %g to i32
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%m_fptosi = fptosi double %m to i32
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%1 = add i32 %g_trunc, %m_fptosi
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ret i32 %1
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}
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define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
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; RV32-ILP32D-LABEL: caller_double_on_stack_exhausted_gprs_fprs:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: addi sp, sp, -16
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; RV32-ILP32D-NEXT: sw ra, 12(sp)
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; RV32-ILP32D-NEXT: lui a0, 262816
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; RV32-ILP32D-NEXT: sw a0, 4(sp)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_0)
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; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI9_0)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_1)
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; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI9_1)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_2)
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; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI9_2)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_3)
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; RV32-ILP32D-NEXT: fld fa3, %lo(.LCPI9_3)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_4)
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; RV32-ILP32D-NEXT: fld fa4, %lo(.LCPI9_4)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_5)
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; RV32-ILP32D-NEXT: fld fa5, %lo(.LCPI9_5)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_6)
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; RV32-ILP32D-NEXT: fld fa6, %lo(.LCPI9_6)(a0)
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_7)
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; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI9_7)(a0)
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; RV32-ILP32D-NEXT: addi a0, zero, 1
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; RV32-ILP32D-NEXT: addi a2, zero, 3
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; RV32-ILP32D-NEXT: addi a4, zero, 5
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; RV32-ILP32D-NEXT: addi a6, zero, 7
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; RV32-ILP32D-NEXT: sw zero, 0(sp)
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; RV32-ILP32D-NEXT: mv a1, zero
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; RV32-ILP32D-NEXT: mv a3, zero
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; RV32-ILP32D-NEXT: mv a5, zero
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; RV32-ILP32D-NEXT: mv a7, zero
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; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs
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; RV32-ILP32D-NEXT: lw ra, 12(sp)
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; RV32-ILP32D-NEXT: addi sp, sp, 16
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; RV32-ILP32D-NEXT: ret
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%1 = call i32 @callee_double_on_stack_exhausted_gprs_fprs(
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i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i64 7, double 8.0,
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double 9.0, double 10.0, double 11.0, double 12.0, double 13.0)
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ret i32 %1
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}
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define double @callee_double_ret() nounwind {
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; RV32-ILP32D-LABEL: callee_double_ret:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI10_0)
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; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI10_0)(a0)
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; RV32-ILP32D-NEXT: ret
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ret double 1.0
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}
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define i32 @caller_double_ret() nounwind {
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; RV32-ILP32D-LABEL: caller_double_ret:
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; RV32-ILP32D: # %bb.0:
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; RV32-ILP32D-NEXT: addi sp, sp, -16
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; RV32-ILP32D-NEXT: sw ra, 12(sp)
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; RV32-ILP32D-NEXT: call callee_double_ret
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; RV32-ILP32D-NEXT: fsd fa0, 0(sp)
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; RV32-ILP32D-NEXT: lw a0, 0(sp)
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; RV32-ILP32D-NEXT: lw ra, 12(sp)
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; RV32-ILP32D-NEXT: addi sp, sp, 16
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; RV32-ILP32D-NEXT: ret
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%1 = call double @callee_double_ret()
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%2 = bitcast double %1 to i64
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%3 = trunc i64 %2 to i32
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ret i32 %3
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}
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