9d172c8e9c
This switches to using DSE + MemorySSA by default again, after fixing the issues reported after the first commit. Notable fixesfc82006331,a0017c2bc2. This reverts commit3a59628f3c.
49 lines
1.3 KiB
LLVM
49 lines
1.3 KiB
LLVM
; RUN: opt -S -basic-aa -dse < %s | FileCheck %s
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; We conservative choose to prevent dead store elimination
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; across release or stronger fences. It's not required
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; (since the must still be a race on %addd.i), but
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; it is conservatively correct. A legal optimization
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; could hoist the second store above the fence, and then
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; DSE one of them.
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define void @test1(i32* %addr.i) {
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; CHECK-LABEL: @test1
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; CHECK: store i32 5
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; CHECK: fence
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; CHECK: store i32 5
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; CHECK: ret
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store i32 5, i32* %addr.i, align 4
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fence release
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store i32 5, i32* %addr.i, align 4
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ret void
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}
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; Same as previous, but with different values. If we ever optimize
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; this more aggressively, this allows us to check that the correct
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; store is retained (the 'i32 1' store in this case)
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define void @test1b(i32* %addr.i) {
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; CHECK-LABEL: @test1b
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; CHECK: store i32 42
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; CHECK: fence release
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; CHECK: store i32 1
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; CHECK: ret
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store i32 42, i32* %addr.i, align 4
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fence release
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store i32 1, i32* %addr.i, align 4
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ret void
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}
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; We *could* DSE across this fence, but don't. No other thread can
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; observe the order of the acquire fence and the store.
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define void @test2(i32* %addr.i) {
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; CHECK-LABEL: @test2
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; CHECK: store
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; CHECK: fence
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; CHECK: store
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; CHECK: ret
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store i32 5, i32* %addr.i, align 4
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fence acquire
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store i32 5, i32* %addr.i, align 4
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ret void
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}
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