39379916a7
The intrinsics were already supported and vector.transfer_read/write lowered direclty into these operations. By providing them as individual ops, however, clients can used them directly, and it opens up progressively lowering transfer operations at higher levels (rather than direct lowering to LLVM IR as done now). Reviewed By: bkramer Differential Revision: https://reviews.llvm.org/D85357
67 lines
2.3 KiB
MLIR
67 lines
2.3 KiB
MLIR
// RUN: mlir-opt %s -convert-scf-to-std -convert-vector-to-llvm -convert-std-to-llvm | \
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// RUN: mlir-cpu-runner -e entry -entry-point-result=void \
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// RUN: -shared-libs=%mlir_integration_test_dir/libmlir_c_runner_utils%shlibext | \
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// RUN: FileCheck %s
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func @maskedload16(%base: memref<?xf32>, %mask: vector<16xi1>,
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%pass_thru: vector<16xf32>) -> vector<16xf32> {
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%ld = vector.maskedload %base, %mask, %pass_thru
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: memref<?xf32>, vector<16xi1>, vector<16xf32> into vector<16xf32>
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return %ld : vector<16xf32>
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}
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func @entry() {
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// Set up memory.
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%c0 = constant 0: index
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%c1 = constant 1: index
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%c16 = constant 16: index
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%A = alloc(%c16) : memref<?xf32>
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scf.for %i = %c0 to %c16 step %c1 {
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%i32 = index_cast %i : index to i32
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%fi = sitofp %i32 : i32 to f32
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store %fi, %A[%i] : memref<?xf32>
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}
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// Set up pass thru vector.
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%u = constant -7.0: f32
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%pass = vector.broadcast %u : f32 to vector<16xf32>
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// Set up masks.
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%f = constant 0: i1
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%t = constant 1: i1
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%none = vector.constant_mask [0] : vector<16xi1>
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%all = vector.constant_mask [16] : vector<16xi1>
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%some = vector.constant_mask [8] : vector<16xi1>
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%0 = vector.insert %f, %some[0] : i1 into vector<16xi1>
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%1 = vector.insert %t, %0[13] : i1 into vector<16xi1>
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%2 = vector.insert %t, %1[14] : i1 into vector<16xi1>
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%other = vector.insert %t, %2[14] : i1 into vector<16xi1>
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//
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// Masked load tests.
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//
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%l1 = call @maskedload16(%A, %none, %pass)
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: (memref<?xf32>, vector<16xi1>, vector<16xf32>) -> (vector<16xf32>)
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vector.print %l1 : vector<16xf32>
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// CHECK: ( -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7, -7 )
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%l2 = call @maskedload16(%A, %all, %pass)
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: (memref<?xf32>, vector<16xi1>, vector<16xf32>) -> (vector<16xf32>)
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vector.print %l2 : vector<16xf32>
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// CHECK: ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 )
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%l3 = call @maskedload16(%A, %some, %pass)
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: (memref<?xf32>, vector<16xi1>, vector<16xf32>) -> (vector<16xf32>)
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vector.print %l3 : vector<16xf32>
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// CHECK: ( 0, 1, 2, 3, 4, 5, 6, 7, -7, -7, -7, -7, -7, -7, -7, -7 )
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%l4 = call @maskedload16(%A, %other, %pass)
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: (memref<?xf32>, vector<16xi1>, vector<16xf32>) -> (vector<16xf32>)
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vector.print %l4 : vector<16xf32>
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// CHECK: ( -7, 1, 2, 3, 4, 5, 6, 7, -7, -7, -7, -7, -7, 13, 14, -7 )
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return
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}
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