caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
54ab9541492d808ae4cf9130dd052d602b78ee32
clang-p2996/llvm/lib/Target/RISCV
History
Amara Emerson 41e9c4b88c [NFC][Outliner] Delete default ctors for Candidate & OutlinedFunction. 
I think it's good practice to avoid having default ctors unless they're really
valid/useful. For OutlinedFunction the default ctor was used to represent a
bail-out value for getOutliningCandidateInfo(), so I changed the API to return
an optional<getOutliningCandidateInfo> instead which seems a tad cleaner.

Differential Revision: https://reviews.llvm.org/D146375
2023-03-20 11:17:10 -07:00
..
AsmParser
[RISCV] Merge getLoadFP*Imm into a single function.
2023-03-14 13:11:11 -07:00
Disassembler
[RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
2023-02-24 21:40:42 +01:00
GISel
…
MCA
…
MCTargetDesc
[RISCV][MC] Adjust conditions to emit R_RISCV_ADD*/R_RISCV_SUB* pairs
2023-03-14 15:17:38 -07:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add new pass to transform undef to pseudo for vector values.
2023-02-22 04:03:22 -08:00
RISCV.h
[RISCV] Add new pass to transform undef to pseudo for vector values.
2023-02-22 04:03:22 -08:00
RISCV.td
[RISCV] Move Processors and Features from RISCV.td to their own files.
2023-01-23 10:17:08 -08:00
RISCVAsmPrinter.cpp
[RISCV][MC][NFC] Refactor RISCVAsmPrinter::PrintAsmMemoryOperand to use early return
2023-03-16 15:02:53 +00:00
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Add asserts that we don't increase codesize during pseudo expansion
2023-01-31 07:49:54 -08:00
RISCVExpandPseudoInsts.cpp
[RISCV] Add asserts that we don't increase codesize during pseudo expansion
2023-01-31 07:49:54 -08:00
RISCVFeatures.td
[Target][RISCV] Update SubtargetFeature definition for RV32/RV64 (NFCI).
2023-03-17 08:49:45 +01:00
RISCVFrameLowering.cpp
[codegen][riscv] Emit CFI directives when using shadow call stack
2023-03-15 17:10:23 +00:00
RISCVFrameLowering.h
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
2023-01-06 09:54:19 -08:00
RISCVGatherScatterLowering.cpp
[NFC] Use TypeSize::geFixedValue() instead of TypeSize::getFixedSize()
2023-01-11 16:49:38 +00:00
RISCVInsertVSETVLI.cpp
[RISCV][InsertVSETVLI] Handle partially transparent instructions in PRE
2023-01-27 11:52:09 -08:00
RISCVInstrFormats.td
[RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
2023-02-15 13:03:31 -08:00
RISCVInstrFormatsC.td
[RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
2023-02-15 13:03:31 -08:00
RISCVInstrFormatsV.td
…
RISCVInstrInfo.cpp
[NFC][Outliner] Delete default ctors for Candidate & OutlinedFunction.
2023-03-20 11:17:10 -07:00
RISCVInstrInfo.h
[NFC][Outliner] Delete default ctors for Candidate & OutlinedFunction.
2023-03-20 11:17:10 -07:00
RISCVInstrInfo.td
[RISCV] Add explicit i64 to isel patterns to reduce RISCVGenDAGISel.inc size.
2023-02-25 20:07:41 -08:00
RISCVInstrInfoA.td
[RISCV] Add explicit i64 to isel patterns to reduce RISCVGenDAGISel.inc size.
2023-02-25 20:07:41 -08:00
RISCVInstrInfoC.td
[RISCV][NFC] Add missing immediate operand types.
2023-02-17 15:56:32 +03:00
RISCVInstrInfoD.td
[RISCV] Move all isel cases for ISD::ConstantFP into RISCVDAGToDAGISel::Select.
2023-02-04 17:31:39 -08:00
RISCVInstrInfoF.td
[RISCV] Remove Commutable property from Zfa fltq/fleq instructions.
2023-02-19 11:37:23 -08:00
RISCVInstrInfoM.td
…
RISCVInstrInfoV.td
[RISCV][CodeGen] Account for LMUL from VS2 for Vector Reduction Instructions
2023-02-07 17:43:23 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Be more explicit string replacements in RISCVInstrInfoVPseudos.td. NFC
2023-02-22 12:56:16 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
2023-03-15 07:47:16 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
2023-03-15 07:47:16 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVInstrInfoXVentana.td
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVInstrInfoZb.td
[RISCV] Add explicit i64 to reduce RISCVGenDAGISel.inc size.
2023-02-25 10:07:26 -08:00
RISCVInstrInfoZc.td
[RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
2023-02-15 13:03:31 -08:00
RISCVInstrInfoZfa.td
[RISCV] Add isReMaterializable to FLI instructions.
2023-03-17 12:16:37 -07:00
RISCVInstrInfoZfh.td
[RISCV] Make Zfh PseudoQuietFCMP definitions predicated on HasStdExtZfh
2023-03-20 17:05:48 +00:00
RISCVInstrInfoZicbo.td
…
RISCVInstrInfoZk.td
…
RISCVISelDAGToDAG.cpp
[RISCV] Support Zfa fli instructions with vector splats.
2023-03-10 09:16:21 -08:00
RISCVISelDAGToDAG.h
[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
2023-02-25 12:05:48 -08:00
RISCVISelLowering.cpp
[RISCV]Optimize (riscvisd::select_cc x, 0, ne, x, 1)
2023-03-16 10:56:26 +08:00
RISCVISelLowering.h
[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
2023-03-15 07:47:16 +08:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
CodeGen: Don't lazily construct MachineFunctionInfo
2022-12-21 10:49:32 -05:00
RISCVMacroFusion.cpp
…
RISCVMacroFusion.h
…
RISCVMakeCompressible.cpp
…
RISCVMCInstLower.cpp
…
RISCVMergeBaseOffset.cpp
…
RISCVProcessors.td
[RISCV] Move Processors and Features from RISCV.td to their own files.
2023-01-23 10:17:08 -08:00
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[CodeGen] Make more use of MachineOperand::getOperandNo. NFC.
2023-02-07 11:50:57 +00:00
RISCVRegisterInfo.h
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
2023-01-06 09:54:19 -08:00
RISCVRegisterInfo.td
[RISCV] Add CoveredBySubRegs to the X*_PD register class.
2023-02-02 10:03:33 -08:00
RISCVRVVInitUndef.cpp
[RISCV] Add new pass to transform undef to pseudo for vector values.
2023-02-22 04:03:22 -08:00
RISCVSchedRocket.td
…
RISCVSchedSiFive7.td
…
RISCVSchedSyntacoreSCR1.td
…
RISCVSchedule.td
…
RISCVScheduleV.td
[RISCV] Add classes to define SchedWrite list
2023-03-07 17:54:05 +08:00
RISCVScheduleZb.td
…
RISCVSExtWRemoval.cpp
[RISCV] Fix miscompile in SExtWRemoval due to early return ignoring other sources
2023-02-08 11:45:48 -08:00
RISCVStripWSuffix.cpp
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
RISCVSubtarget.cpp
[RISCV] Enable subregister liveness by default
2023-03-08 23:03:35 -08:00
RISCVSubtarget.h
[Target][RISCV] Update SubtargetFeature definition for RV32/RV64 (NFCI).
2023-03-17 08:49:45 +01:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[RISCV] Fix regression due to interaction of MachineOutliner and MachineCopyPropagation
2023-03-14 17:55:11 +00:00
RISCVTargetMachine.h
CodeGen: Don't lazily construct MachineFunctionInfo
2022-12-21 10:49:32 -05:00
RISCVTargetObjectFile.cpp
[MC][CodeGen] Define R_RISCV_PLT32 and lower dso_local_equivalent to it
2023-02-23 01:26:27 +00:00
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Enable interleaved access vectorization
2023-03-16 15:48:55 +00:00
RISCVTargetTransformInfo.h
[RISCV] Enable interleaved access vectorization
2023-03-16 15:48:55 +00:00