Abhilash Majumder 55f3df875d [NVPTX] Fix and refine prefetch.* intrinsics (#126899) ...

This is follow-up PR from #125887  which fixes the intrinsic failures .

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Co-authored-by: abmajumder <abmajumder@nvidia.com>

2025-02-13 17:54:01 +01:00

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AArch64

Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)

2025-02-12 18:54:39 +05:30

AMDGPU

[AMDGPU] Fix llvm.amdgcn.workitem.id-unsupported-calling-convention.ll (#127041)

2025-02-13 22:23:47 +07:00

ARC

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ARM

Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126684)

2025-02-12 18:54:39 +05:30

AVR

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BPF

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CSKY

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DirectX

[DirectX] Set Shader Flag DisableOptimizations (#126813)

2025-02-12 16:45:01 -05:00

Generic

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Hexagon

[RDF] Create phi nodes for clobbering defs (#123694)

2025-02-07 08:28:29 -06:00

Inputs

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Lanai

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LoongArch

[LoongArch] Add test for stackmaps. NFC

2025-02-13 20:58:26 +08:00

M68k

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Mips

Revert "[Mips] Support llvm.readcyclecounter intrinsic (#114953)"

2025-02-11 14:37:17 +08:00

MIR

MachineCopyPropagation: Do not remove copies preserved by regmask (#125868)

2025-02-10 12:26:33 -05:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Fix and refine prefetch.* intrinsics (#126899)

2025-02-13 17:54:01 +01:00

PowerPC

[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (#116984)

2025-02-13 09:09:17 -05:00

RISCV

[RISCV] Default to MicroOpBufferSize = 1 for scheduling purposes (#126608)

2025-02-12 12:31:39 -08:00

SPARC

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SPIRV

[SPIR-V] Type inference must realize that a <1 x Type> vector type is not a legal vector type in LLT (#124560)

2025-02-13 17:46:42 +01:00

SystemZ

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Thumb

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Thumb2

[ARM] Fix calling convention for __fp16 with big-endian (#126741)

2025-02-13 09:09:29 +00:00

VE

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WebAssembly

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WinCFGuard

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WinEH

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X86

[X86] Fold EXTRACT_SUBVECTOR(VPERMV(V,M),C) -> EXTRACT_SUBVECTOR(VPERMV(V,M'),0)

2025-02-13 12:35:05 +00:00

XCore

[llvm] Remove br i1 undef in some llvm/test/CodeGen tests (#126811)

2025-02-12 09:19:00 +00:00

Xtensa

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