6c452834a1
This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
74 lines
2.7 KiB
YAML
74 lines
2.7 KiB
YAML
# RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s
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# https://bugs.llvm.org/show_bug.cgi?id=33620
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---
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# This would assert due to the empty live interval created for %vreg9
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# on the last S_NOP with an undef subreg use.
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# CHECK-LABEL: name: expecting_non_empty_interval
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# CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit %exec
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# CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 8 into %stack.0, align 4)
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# CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit %exec
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# CHECK-NEXT: dead %2:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit %exec
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# CHECK: S_NOP 0, implicit %6.sub1
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# CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 8 from %stack.0, align 4)
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# CHECK-NEXT: S_NOP 0, implicit %8.sub1
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# CHECK-NEXT: S_NOP 0, implicit undef %9.sub0
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name: expecting_non_empty_interval
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_64, preferred-register: '' }
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- { id: 1, class: vgpr_32, preferred-register: '' }
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- { id: 2, class: vgpr_32, preferred-register: '' }
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- { id: 3, class: vreg_64, preferred-register: '' }
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body: |
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bb.0:
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successors: %bb.1
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undef %0.sub1 = V_MAC_F32_e32 0, undef %1, undef %0.sub1, implicit %exec
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undef %3.sub1 = V_MOV_B32_e32 1786773504, implicit %exec
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dead %2 = V_MUL_F32_e32 0, %3.sub1, implicit %exec
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bb.1:
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S_NOP 0, implicit %3.sub1
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S_NOP 0, implicit %0.sub1
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S_NOP 0, implicit undef %0.sub0
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...
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# Similar assert which happens when trying to rematerialize.
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# https://bugs.llvm.org/show_bug.cgi?id=33884
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---
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# CHECK-LABEL: name: rematerialize_empty_interval_has_reference
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# CHECK-NOT: MOV
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# CHECK: undef %3.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit %exec
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# CHECK: bb.1:
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# CHECK-NEXT: S_NOP 0, implicit %3.sub2
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# CHECK-NEXT: S_NOP 0, implicit undef %6.sub0
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# CHECK-NEXT: undef %4.sub2:vreg_128 = V_MOV_B32_e32 0, implicit %exec
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# CHECK-NEXT: S_NOP 0, implicit %4.sub2
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name: rematerialize_empty_interval_has_reference
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_128, preferred-register: '' }
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- { id: 1, class: vgpr_32, preferred-register: '' }
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- { id: 2, class: vgpr_32, preferred-register: '' }
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- { id: 3, class: vreg_128, preferred-register: '' }
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body: |
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bb.0:
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successors: %bb.1
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undef %0.sub2 = V_MOV_B32_e32 0, implicit %exec
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undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit %exec
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bb.1:
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S_NOP 0, implicit %3.sub2
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S_NOP 0, implicit undef %0.sub0
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S_NOP 0, implicit %0.sub2
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...
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