78cb4562fa
This patch carries forward our aim to remove offset field from qRegisterInfo packets and XML register description. I have created a new function which returns if offset fields are dynamic meaning client can calculate offset on its own based on register number sequence and register size. For now this function only returns true for NativeRegisterContextLinux_arm64 but we can test this for other architectures and make it standard later. As a consequence we do not send offset field from lldb-server (arm64 for now) while other stubs dont have an offset field so it wont effect them for now. On the client side we have replaced previous offset calculation algorithm with a new scheme, where we sort all primary registers in increasing order of remote regnum and then calculate offset incrementally. This committ also includes a test to verify all of above functionality on Arm64. Reviewed By: labath Differential Revision: https://reviews.llvm.org/D91241
152 lines
8.5 KiB
Python
152 lines
8.5 KiB
Python
from __future__ import print_function
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from textwrap import dedent
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import lldb
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test.decorators import *
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from gdbclientutils import *
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class MyResponder(MockGDBServerResponder):
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def qXferRead(self, obj, annex, offset, length):
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if annex == "target.xml":
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return dedent("""\
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<?xml version="1.0"?>
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<target version="1.0">
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<architecture>aarch64</architecture>
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<feature name="org.gnu.gdb.aarch64.core">
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<reg name="cpsr" regnum="33" bitsize="32"/>
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<reg name="x0" regnum="0" bitsize="64"/>
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<reg name="x1" bitsize="64"/>
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<reg name="x2" bitsize="64"/>
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<reg name="x3" bitsize="64"/>
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<reg name="x4" bitsize="64"/>
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<reg name="x5" bitsize="64"/>
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<reg name="x6" bitsize="64"/>
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<reg name="x7" bitsize="64"/>
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<reg name="x8" bitsize="64"/>
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<reg name="x9" bitsize="64"/>
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<reg name="x10" bitsize="64"/>
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<reg name="x11" bitsize="64"/>
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<reg name="x12" bitsize="64"/>
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<reg name="x13" bitsize="64"/>
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<reg name="x14" bitsize="64"/>
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<reg name="x15" bitsize="64"/>
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<reg name="x16" bitsize="64"/>
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<reg name="x17" bitsize="64"/>
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<reg name="x18" bitsize="64"/>
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<reg name="x19" bitsize="64"/>
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<reg name="x20" bitsize="64"/>
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<reg name="x21" bitsize="64"/>
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<reg name="x22" bitsize="64"/>
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<reg name="x23" bitsize="64"/>
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<reg name="x24" bitsize="64"/>
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<reg name="x25" bitsize="64"/>
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<reg name="x26" bitsize="64"/>
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<reg name="x27" bitsize="64"/>
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<reg name="x28" bitsize="64"/>
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<reg name="x29" bitsize="64"/>
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<reg name="x30" bitsize="64"/>
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<reg name="sp" bitsize="64"/>
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<reg name="pc" bitsize="64"/>
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<reg name="w0" bitsize="32" value_regnums="0" invalidate_regnums="0" regnum="34"/>
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<reg name="w1" bitsize="32" value_regnums="1" invalidate_regnums="1"/>
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<reg name="w2" bitsize="32" value_regnums="2" invalidate_regnums="2"/>
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<reg name="w3" bitsize="32" value_regnums="3" invalidate_regnums="3"/>
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<reg name="w4" bitsize="32" value_regnums="4" invalidate_regnums="4"/>
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<reg name="w5" bitsize="32" value_regnums="5" invalidate_regnums="5"/>
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<reg name="w6" bitsize="32" value_regnums="6" invalidate_regnums="6"/>
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<reg name="w7" bitsize="32" value_regnums="7" invalidate_regnums="7"/>
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<reg name="w8" bitsize="32" value_regnums="8" invalidate_regnums="8"/>
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<reg name="w9" bitsize="32" value_regnums="9" invalidate_regnums="9"/>
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<reg name="w10" bitsize="32" value_regnums="10" invalidate_regnums="10"/>
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<reg name="w11" bitsize="32" value_regnums="11" invalidate_regnums="11"/>
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<reg name="w12" bitsize="32" value_regnums="12" invalidate_regnums="12"/>
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<reg name="w13" bitsize="32" value_regnums="13" invalidate_regnums="13"/>
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<reg name="w14" bitsize="32" value_regnums="14" invalidate_regnums="14"/>
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<reg name="w15" bitsize="32" value_regnums="15" invalidate_regnums="15"/>
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<reg name="w16" bitsize="32" value_regnums="16" invalidate_regnums="16"/>
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<reg name="w17" bitsize="32" value_regnums="17" invalidate_regnums="17"/>
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<reg name="w18" bitsize="32" value_regnums="18" invalidate_regnums="18"/>
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<reg name="w19" bitsize="32" value_regnums="19" invalidate_regnums="19"/>
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<reg name="w20" bitsize="32" value_regnums="20" invalidate_regnums="20"/>
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<reg name="w21" bitsize="32" value_regnums="21" invalidate_regnums="21"/>
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<reg name="w22" bitsize="32" value_regnums="22" invalidate_regnums="22"/>
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<reg name="w23" bitsize="32" value_regnums="23" invalidate_regnums="23"/>
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<reg name="w24" bitsize="32" value_regnums="24" invalidate_regnums="24"/>
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<reg name="w25" bitsize="32" value_regnums="25" invalidate_regnums="25"/>
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<reg name="w26" bitsize="32" value_regnums="26" invalidate_regnums="26"/>
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<reg name="w27" bitsize="32" value_regnums="27" invalidate_regnums="27"/>
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<reg name="w28" bitsize="32" value_regnums="28" invalidate_regnums="28"/>
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</feature>
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</target>
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"""), False
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else:
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return None,
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def readRegister(self, regnum):
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return "E01"
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def readRegisters(self):
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return "20000000000000002000000000000000f0c154bfffff00005daa985a8fea0b48f0b954bfffff0000ad13cce570150b48380000000000000070456abfffff0000a700000000000000000000000000000001010101010101010000000000000000f0c154bfffff00000f2700000000000008e355bfffff0000080e55bfffff0000281041000000000010de61bfffff00005c05000000000000f0c154bfffff000090fcffffffff00008efcffffffff00008ffcffffffff00000000000000000000001000000000000090fcffffffff000000d06cbfffff0000f0c154bfffff00000100000000000000d0b954bfffff0000e407400000000000d0b954bfffff0000e40740000000000000100000"
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class TestAArch64XMLRegOffsets(GDBRemoteTestBase):
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@skipIfXmlSupportMissing
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@skipIfRemote
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@skipIfLLVMTargetMissing("AArch64")
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def test_register_gpacket_offsets(self):
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"""
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Test that we correctly associate the register info with the eh_frame
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register numbers.
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"""
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target = self.createTarget("basic_eh_frame-aarch64.yaml")
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self.server.responder = MyResponder()
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if self.TraceOn():
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self.runCmd("log enable gdb-remote packets")
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self.addTearDownHook(
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lambda: self.runCmd("log disable gdb-remote packets"))
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process = self.connect(target)
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lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
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[lldb.eStateStopped])
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registerSet = process.GetThreadAtIndex(
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0).GetFrameAtIndex(0).GetRegisters().GetValueAtIndex(0)
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reg_val_dict = {
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"x0": 0x0000000000000020, "x1": 0x0000000000000020,
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"x2": 0x0000ffffbf54c1f0, "x3": 0x480bea8f5a98aa5d,
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"x4": 0x0000ffffbf54b9f0, "x5": 0x480b1570e5cc13ad,
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"x6": 0x0000000000000038, "x7": 0x0000ffffbf6a4570,
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"x8": 0x00000000000000a7, "x9": 0x0000000000000000,
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"x10": 0x0101010101010101, "x11": 0x0000000000000000,
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"x12": 0x0000ffffbf54c1f0, "x13": 0x000000000000270f,
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"x14": 0x0000ffffbf55e308, "x15": 0x0000ffffbf550e08,
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"x16": 0x0000000000411028, "x17": 0x0000ffffbf61de10,
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"x18": 0x000000000000055c, "x19": 0x0000ffffbf54c1f0,
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"x20": 0x0000fffffffffc90, "x21": 0x0000fffffffffc8e,
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"x22": 0x0000fffffffffc8f, "x23": 0x0000000000000000,
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"x24": 0x0000000000001000, "x25": 0x0000fffffffffc90,
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"x26": 0x0000ffffbf6cd000, "x27": 0x0000ffffbf54c1f0,
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"x28": 0x0000000000000001, "x29": 0x0000ffffbf54b9d0,
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"x30": 0x00000000004007e4, "sp": 0x0000ffffbf54b9d0,
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"pc": 0x00000000004007e4, "cpsr": 0x00001000, "w0": 0x00000020,
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"w1": 0x00000020, "w2": 0xbf54c1f0, "w3": 0x5a98aa5d,
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"w4": 0xbf54b9f0, "w5": 0xe5cc13ad, "w6": 0x00000038,
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"w7": 0xbf6a4570, "w8": 0x000000a7, "w9": 0x00000000,
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"w10": 0x01010101, "w11": 0x00000000, "w12": 0xbf54c1f0,
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"w13": 0x0000270f, "w14": 0xbf55e308, "w15": 0xbf550e08,
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"w16": 0x00411028, "w17": 0xbf61de10, "w18": 0x0000055c,
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"w19": 0xbf54c1f0, "w20": 0xfffffc90, "w21": 0xfffffc8e,
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"w22": 0xfffffc8f, "w23": 0x00000000, "w24": 0x00001000,
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"w25": 0xfffffc90, "w26": 0xbf6cd000, "w27": 0xbf54c1f0,
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"w28": 0x00000001
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}
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for reg in registerSet:
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self.assertEqual(reg.GetValueAsUnsigned(),
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reg_val_dict[reg.GetName()])
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